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Searched +full:spi +full:- +full:max +full:- +full:frequency (Results 1 – 25 of 174) sorted by relevance

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/Documentation/devicetree/bindings/iio/resolver/
Dad2s90.txt1 Analog Devices AD2S90 Resolver-to-Digital Converter
6 - compatible: should be "adi,ad2s90"
7 - reg: SPI chip select number for the device
8 - spi-max-frequency: set maximum clock frequency, must be 830000
9 - spi-cpol and spi-cpha:
10 Either SPI mode (0,0) or (1,1) must be used, so specify none or both of
11 spi-cpha, spi-cpol.
14 Documentation/devicetree/bindings/spi/spi-bus.txt
16 Note about max frequency:
17 Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns
[all …]
/Documentation/devicetree/bindings/spi/
Dqcom,spi-qup.txt1 Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
6 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
10 - compatible: Should contain:
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
15 - reg: Should contain base register location and length
16 - interrupts: Interrupt number used by this controller
18 - clocks: Should contain the core clock and the AHB clock.
[all …]
Dspi-stm32-qspi.txt4 - compatible: should be "st,stm32f469-qspi"
5 - reg: the first contains the register location and length.
7 - reg-names: should contain the reg names "qspi" "qspi_mm"
8 - interrupts: should contain the interrupt for the device
9 - clocks: the phandle of the clock needed by the QSPI controller
10 - A pinctrl must be defined to set pins in mode of operation for QSPI transfer
13 - resets: must contain the phandle to the reset controller.
15 A spi flash (NOR/NAND) must be a child of spi node and could have some
16 properties. Also see jedec,spi-nor.txt.
19 - reg: chip-Select number (QSPI controller may connect 2 flashes)
[all …]
/Documentation/devicetree/bindings/net/wireless/
Dti,wlcore,spi.txt3 The wl12xx/wl18xx chips can be connected via SPI or via SDIO. This
4 document describes the binding for the SPI connected chip.
7 - compatible : Should be one of the following:
18 - reg : Chip select address of device
19 - spi-max-frequency : Maximum SPI clocking speed of device in Hz
20 - interrupts : Should contain parameters for 1 interrupt line.
21 - vwlan-supply : Point the node of the regulator that powers/enable the
25 - ref-clock-frequency : Reference clock frequency (should be set for wl12xx)
26 - clock-xtal : boolean, clock is generated from XTAL
28 - Please consult Documentation/devicetree/bindings/spi/spi-bus.txt
[all …]
/Documentation/devicetree/bindings/iio/dac/
Dltc1660.txt1 * Linear Technology Micropower octal 8-Bit and 10-Bit DACs
4 - compatible: Must be one of the following:
7 - reg: SPI chip select number for the device
8 - vref-supply: Phandle to the voltage reference supply
11 - spi-max-frequency: Definition as per
12 Documentation/devicetree/bindings/spi/spi-bus.txt.
13 Max frequency for this chip is 5 MHz.
19 spi-max-frequency = <5000000>;
20 vref-supply = <&vref_reg>;
Dti,dac7311.txt4 - compatible: must be set to:
8 - reg: spi chip select number for the device
9 - vref-supply: The regulator supply for ADC reference voltage
12 - spi-max-frequency: Max SPI frequency to use
20 spi-max-frequency = <1000000>;
21 vref-supply = <&vdd_supply>;
Dad7303.txt4 - compatible: Must be "adi,ad7303"
5 - reg: SPI chip select number for the device
6 - spi-max-frequency: Max SPI frequency to use (< 30000000)
7 - Vdd-supply: Phandle to the Vdd power supply
10 - REF-supply: Phandle to the external reference voltage supply. This should
19 spi-max-frequency = <10000000>;
20 Vdd-supply = <&vdd_supply>;
21 adi,use-external-reference;
22 REF-supply = <&vref_supply>;
/Documentation/devicetree/bindings/iio/adc/
Dti-adc0832.txt4 - compatible: Should be one of
9 - reg: spi chip select number for the device
10 - vref-supply: The regulator supply for ADC reference voltage
11 - spi-max-frequency: Max SPI frequency to use (< 400000)
17 vref-supply = <&vdd_supply>;
18 spi-max-frequency = <200000>;
Dmcp3911.txt4 - compatible: Should be "microchip,mcp3911"
5 - reg: SPI chip select number for the device
8 - spi-max-frequency: Definition as per
9 Documentation/devicetree/bindings/spi/spi-bus.txt.
10 Max frequency for this chip is 20MHz.
13 - clocks: Phandle and clock identifier for sampling clock
14 - interrupt-parent: Phandle to the parent interrupt controller
15 - interrupts: IRQ line for the ADC
16 - microchip,device-addr: Device address when multiple MCP3911 chips are present on the
17 same SPI bus. Valid values are 0-3. Defaults to 0.
[all …]
Dti-adc084s021.txt4 - compatible : Must be "ti,adc084s021"
5 - reg : SPI chip select number for the device
6 - vref-supply : The regulator supply for ADC reference voltage
7 - spi-cpol : Per spi-bus bindings
8 - spi-cpha : Per spi-bus bindings
9 - spi-max-frequency : Per spi-bus bindings
15 vref-supply = <&adc_vref>;
16 spi-cpol;
17 spi-cpha;
18 spi-max-frequency = <16000000>;
Dti-ads124s08.txt4 - compatible :
7 - reg : spi chip select number for the device
10 - spi-max-frequency : Definition as per
11 Documentation/devicetree/bindings/spi/spi-bus.txt
12 - spi-cpha : Definition as per
13 Documentation/devicetree/bindings/spi/spi-bus.txt
16 - reset-gpios : GPIO pin used to reset the device.
22 spi-max-frequency = <1000000>;
23 spi-cpha;
24 reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
Dmax11100.txt4 - compatible: Should be "maxim,max11100"
5 - reg: the adc unit address
6 - vref-supply: phandle to the regulator that provides reference voltage
9 - spi-max-frequency: SPI maximum frequency
16 vref-supply = <&adc0_vref>;
17 spi-max-frequency = <240000>;
/Documentation/devicetree/bindings/security/tpm/
Dtpm_tis_spi.txt2 - compatible: should be one of the following
3 "st,st33htpm-spi"
5 "tcg,tpm_tis-spi"
6 - spi-max-frequency: Maximum SPI frequency (depends on TPMs).
9 - pinctrl-names: Contains only one value - "default".
10 - pintctrl-0: Specifies the pin control groups used for this controller.
12 Example (for ARM-based BeagleBoard xM with TPM_TIS on SPI4):
19 compatible = "tcg,tpm_tis-spi";
21 spi-max-frequency = <10000000>;
/Documentation/devicetree/bindings/iio/temperature/
Dmax31856.txt6 - thermocouple-type: Type of thermocouple (THERMOCOUPLE_TYPE_K if
10 - compatible: must be "maxim,max31856"
11 - reg: SPI chip select number for the device
12 - spi-max-frequency: As per datasheet max. supported freq is 5000000
13 - spi-cpha: must be defined for max31856 to enable SPI mode 1
15 Refer to spi/spi-bus.txt for generic SPI slave bindings.
18 temp-sensor@0 {
21 spi-max-frequency = <5000000>;
22 spi-cpha;
23 thermocouple-type = <THERMOCOUPLE_TYPE_K>;
Dmaxim_thermocouple.txt8 - compatible: must be "maxim,max31855" or "maxim,max6675"
9 - reg: SPI chip select number for the device
10 - spi-max-frequency: must be 4300000
11 - spi-cpha: must be defined for max6675 to enable SPI mode 1
13 Refer to spi/spi-bus.txt for generic SPI slave bindings.
20 spi-max-frequency = <4300000>;
/Documentation/devicetree/bindings/eeprom/
Dat25.txt1 EEPROMs (SPI) compatible with Atmel at25.
4 - compatible : Should be "<vendor>,<type>", and generic value "atmel,at25".
11 - reg : chip select number
12 - spi-max-frequency : max spi frequency to use
13 - pagesize : size of the eeprom page
14 - size : total eeprom size in bytes
15 - address-width : number of address bits (one of 8, 9, 16, or 24).
20 - spi-cpha : SPI shifted clock phase, as per spi-bus bindings.
21 - spi-cpol : SPI inverse clock polarity, as per spi-bus bindings.
22 - read-only : this parameter-less property disables writes to the eeprom
[all …]
/Documentation/devicetree/bindings/net/nfc/
Dst95hf.txt3 ST NFC Transceiver is required to attach with SPI bus.
4 ST95HF node should be defined in DT as SPI slave device of SPI
11 - reg: Address of SPI slave "ST95HF transceiver" on SPI master bus.
13 - compatible: should be "st,st95hf" for ST95HF NFC transceiver
15 - spi-max-frequency: Max. operating SPI frequency for ST95HF
18 - enable-gpio: GPIO line to enable ST95HF transceiver.
20 - interrupts : Standard way to define ST95HF transceiver's out
25 - st95hfvin-supply : This is an optional property. It contains a
30 spi@9840000 {
32 #address-cells = <1>;
[all …]
/Documentation/devicetree/bindings/mtd/
Daspeed-smc.txt2 * Aspeed SPI Flash Memory Controller
5 three chip selects, two of which are always of SPI type and the third
6 can be SPI or NOR type flash. These bindings only describe SPI.
8 The two SPI flash memory controllers in the AST2500 each support two
12 - compatible : Should be one of
13 "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
15 "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
16 "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
18 - reg : the first contains the control register location and length,
[all …]
Dmicrochip,mchp23k256.txt1 * MTD SPI driver for Microchip 23K256 (and similar) serial SRAM
4 - #address-cells, #size-cells : Must be present if the device has sub-nodes
6 - compatible : Must be one of "microchip,mchp23k256" or "microchip,mchp23lcv1024"
7 - reg : Chip-Select number
8 - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
12 spi-sram@0 {
13 #address-cells = <1>;
14 #size-cells = <1>;
17 spi-max-frequency = <20000000>;
/Documentation/devicetree/bindings/iio/imu/
Dadi,adis16480.txt6 - compatible: Must be one of
11 * "adi,adis16495-1"
12 * "adi,adis16495-2"
13 * "adi,adis16495-3"
14 * "adi,adis16497-1"
15 * "adi,adis16497-2"
16 * "adi,adis16497-3"
17 - reg: SPI chip select number for the device
18 - spi-max-frequency: Max SPI frequency to use
19 see: Documentation/devicetree/bindings/spi/spi-bus.txt
[all …]
/Documentation/devicetree/bindings/fpga/
Dlattice-ice40-fpga-mgr.txt4 - compatible: Should contain "lattice,ice40-fpga-mgr"
5 - reg: SPI chip select
6 - spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
7 - cdone-gpios: GPIO input connected to CDONE pin
8 - reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note
10 FPGA will enter Master SPI mode and drive SCK with a
16 compatible = "lattice,ice40-fpga-mgr";
18 spi-max-frequency = <1000000>;
19 cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
20 reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
/Documentation/devicetree/bindings/misc/
Dlwn-bk4.txt1 * Liebherr's BK4 controller external SPI
5 The SPI is used for data and management purposes in both master and
10 - compatible : Should be "lwn,bk4"
12 Required SPI properties:
14 - reg : Should be address of the device chip select within
17 - spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
22 spidev0: spi@0 {
24 spi-max-frequency = <30000000>;
Dge-achc.txt4 SPI is used for device management.
10 - compatible : Should be "ge,achc"
12 Required SPI properties:
14 - reg : Should be address of the device chip select within
17 - spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
22 spidev0: spi@0 {
25 spi-max-frequency = <1000000>;
/Documentation/devicetree/bindings/iio/proximity/
Das3935.txt4 - compatible: must be "ams,as3935"
5 - reg: SPI chip select number for the device
6 - spi-max-frequency: specifies maximum SPI clock frequency
7 - spi-cpha: SPI Mode 1. Refer to spi/spi-bus.txt for generic SPI
9 - interrupts : the sole interrupt generated by the device
11 Refer to interrupt-controller/interrupts.txt for generic
15 - ams,tuning-capacitor-pf: Calibration tuning capacitor stepping
16 value 0 - 120pF. This will require using the calibration data from
18 - ams,nflwdth: Set the noise and watchdog threshold register on
28 spi-max-frequency = <400000>;
[all …]
/Documentation/devicetree/bindings/net/
Dmaxim,ds26522.txt4 - compatible: Should contain "maxim,ds26522".
5 - reg: SPI CS.
6 - spi-max-frequency: SPI clock.
12 spi-max-frequency = <2000000>; /* input clock */

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