Searched +full:spi +full:- +full:tx +full:- +full:bus +full:- +full:width (Results 1 – 7 of 7) sorted by relevance
| /Documentation/devicetree/bindings/spi/ |
| D | allwinner,sun4i-a10-spi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/allwinner,sun4i-a10-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 SPI Controller Device Tree Bindings
10 - $ref: "spi-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <maxime.ripard@bootlin.com>
17 "#address-cells": true
18 "#size-cells": true
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| D | allwinner,sun6i-a31-spi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/allwinner,sun6i-a31-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 SPI Controller Device Tree Bindings
10 - $ref: "spi-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <maxime.ripard@bootlin.com>
17 "#address-cells": true
18 "#size-cells": true
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| D | spi-stm32-qspi.txt | 4 - compatible: should be "st,stm32f469-qspi"
5 - reg: the first contains the register location and length.
7 - reg-names: should contain the reg names "qspi" "qspi_mm"
8 - interrupts: should contain the interrupt for the device
9 - clocks: the phandle of the clock needed by the QSPI controller
10 - A pinctrl must be defined to set pins in mode of operation for QSPI transfer
13 - resets: must contain the phandle to the reset controller.
15 A spi flash (NOR/NAND) must be a child of spi node and could have some
16 properties. Also see jedec,spi-nor.txt.
19 - reg: chip-Select number (QSPI controller may connect 2 flashes)
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| D | spi-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Generic Binding
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-[0-9a-f])*$"
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| D | qcom,spi-qcom-qspi.txt | 3 The QSPI controller allows SPI protocol communication in single, dual, or quad
7 - compatible: An SoC specific identifier followed by "qcom,qspi-v1", such as
8 "qcom,sdm845-qspi", "qcom,qspi-v1"
9 - reg: Should contain the base register location and length.
10 - interrupts: Interrupt number used by the controller.
11 - clocks: Should contain the core and AHB clock.
12 - clock-names: Should be "core" for core clock and "iface" for AHB clock.
14 SPI slave nodes must be children of the SPI master node and can contain
15 properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
19 qspi: spi@88df000 {
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| D | spi-mxic.txt | 1 Macronix SPI controller Device Tree Bindings
2 --------------------------------------------
5 - compatible: should be "mxicy,mx25f0a-spi"
6 - #address-cells: should be 1
7 - #size-cells: should be 0
8 - reg: should contain 2 entries, one for the registers and one for the direct
10 - reg-names: should contain "regs" and "dirmap"
11 - interrupts: interrupt line connected to the SPI controller
12 - clock-names: should contain "ps_clk", "send_clk" and "send_dly_clk"
13 - clocks: should contain 3 entries for the "ps_clk", "send_clk" and
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| /Documentation/devicetree/bindings/dma/ |
| D | img-mdc-dma.txt | 1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
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