Searched +full:sub +full:- +full:nodes (Results 1 – 25 of 215) sorted by relevance
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| /Documentation/devicetree/bindings/net/ |
| D | marvell-pxa168.txt | 4 - compatible: should be "marvell,pxa168-eth".
5 - reg: address and length of the register set for the device.
6 - interrupts: interrupt for the device.
7 - clocks: pointer to the clock for the device.
10 - port-id: Ethernet port number. Should be '0','1' or '2'.
11 - #address-cells: must be 1 when using sub-nodes.
12 - #size-cells: must be 0 when using sub-nodes.
13 - phy-handle: see ethernet.txt file in the same directory.
18 Sub-nodes:
19 Each PHY can be represented as a sub-node. This is not mandatory.
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | renesas,rzn1-pinctrl.txt | 4 -------------------
6 - compatible: SoC-specific compatible string "renesas,<soc-specific>-pinctrl"
7 followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible
9 "renesas,r9a06g032-pinctrl" for RZ/N1D
10 "renesas,r9a06g033-pinctrl" for RZ/N1S
11 - reg: Address base and length of the memory area where the pin controller
13 - clocks: phandle for the clock, see the description of clock-names below.
14 - clock-names: Contains the name of the clock:
18 pinctrl: pin-controller@40067000 {
19 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
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| D | meson,pinctrl.txt | 4 - compatible: one of "amlogic,meson8-cbus-pinctrl"
5 "amlogic,meson8b-cbus-pinctrl"
6 "amlogic,meson8m2-cbus-pinctrl"
7 "amlogic,meson8-aobus-pinctrl"
8 "amlogic,meson8b-aobus-pinctrl"
9 "amlogic,meson8m2-aobus-pinctrl"
10 "amlogic,meson-gxbb-periphs-pinctrl"
11 "amlogic,meson-gxbb-aobus-pinctrl"
12 "amlogic,meson-gxl-periphs-pinctrl"
13 "amlogic,meson-gxl-aobus-pinctrl"
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| D | renesas,rza1-pinctrl.txt | 5 Pin multiplexing and GPIO configuration is performed on a per-pin basis
6 writing configuration values to per-port register sets.
12 -------------------
15 - compatible: should be:
16 - "renesas,r7s72100-ports": for RZ/A1H
17 - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
18 - "renesas,r7s72102-ports": for RZ/A1L
20 - reg
27 pinctrl: pin-controller@fcfe3000 {
28 compatible = "renesas,r7s72100-ports";
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| D | renesas,rza2-pinctrl.txt | 4 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
10 -------------------
13 - compatible: shall be:
14 - "renesas,r7s9210-pinctrl": for RZ/A2M
15 - reg
18 - gpio-controller
20 - #gpio-cells
22 - gpio-ranges
27 pinctrl: pin-controller@fcffe000 {
28 compatible = "renesas,r7s9210-pinctrl";
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| /Documentation/media/kapi/ |
| D | v4l2-intro.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ------------
7 hardware: most devices have multiple ICs, export multiple device nodes in
8 /dev, and create also non-V4L2 devices such as DVB, ALSA, FB, I2C and input
15 called 'sub-devices'.
18 creating V4L device nodes and video_buf for handling the video buffers
22 connecting to sub-devices themselves. Some of this is quite complicated
32 A good example to look at as a reference is the v4l2-pci-skeleton.c
38 -------------------------
44 2) A way of initializing and commanding sub-devices (if any).
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| D | v4l2-subdev.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 V4L2 sub-devices
4 ----------------
6 Many drivers need to communicate with sub-devices. These devices can do all
8 encoding or decoding. For webcams common sub-devices are sensors and camera
12 driver with a consistent interface to these sub-devices the
13 :c:type:`v4l2_subdev` struct (v4l2-subdev.h) was created.
15 Each sub-device driver must have a :c:type:`v4l2_subdev` struct. This struct
16 can be stand-alone for simple sub-devices or it might be embedded in a larger
18 low-level device struct (e.g. ``i2c_client``) that contains the device data as
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| /Documentation/devicetree/bindings/phy/ |
| D | uniphier-usb2-phy.txt | 7 controller doesn't include its own High-Speed PHY. This needs to specify
8 USB2 PHY instead of USB3 HS-PHY.
11 - compatible: Should contain one of the following:
12 "socionext,uniphier-pro4-usb2-phy" - for Pro4 SoC
13 "socionext,uniphier-ld11-usb2-phy" - for LD11 SoC
15 Sub-nodes:
16 Each PHY should be represented as a sub-node.
18 Sub-nodes required properties:
19 - #phy-cells: Should be 0.
20 - reg: The number of the PHY.
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| D | brcm-sata-phy.txt | 4 - compatible: should be one or more of
5 "brcm,bcm7425-sata-phy"
6 "brcm,bcm7445-sata-phy"
7 "brcm,iproc-ns2-sata-phy"
8 "brcm,iproc-nsp-sata-phy"
9 "brcm,phy-sata3"
10 "brcm,iproc-sr-sata-phy"
11 "brcm,bcm63138-sata-phy"
12 - address-cells: should be 1
13 - size-cells: should be 0
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| D | berlin-sata-phy.txt | 2 ---------------
5 - compatible: should be one of
6 "marvell,berlin2-sata-phy"
7 "marvell,berlin2q-sata-phy"
8 - address-cells: should be 1
9 - size-cells: should be 0
10 - phy-cells: from the generic PHY bindings, must be 1
11 - reg: address and length of the register
12 - clocks: reference to the clock entry
14 Sub-nodes:
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| D | phy-stm32-usbphyc.txt | 14 |_ PHY port#2 ----| |________________
23 - compatible: must be "st,stm32mp1-usbphyc"
24 - reg: address and length of the usb phy control register set
25 - clocks: phandle + clock specifier for the PLL phy clock
26 - #address-cells: number of address cells for phys sub-nodes, must be <1>
27 - #size-cells: number of size cells for phys sub-nodes, must be <0>
30 - assigned-clocks: phandle + clock specifier for the PLL phy clock
31 - assigned-clock-parents: the PLL phy clock parent
32 - resets: phandle + reset specifier
34 Required nodes: one sub-node per port the controller provides.
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| D | rockchip-usb-phy.txt | 4 - compatible: matching the soc type, one of
5 "rockchip,rk3066a-usb-phy"
6 "rockchip,rk3188-usb-phy"
7 "rockchip,rk3288-usb-phy"
8 - #address-cells: should be 1
9 - #size-cells: should be 0
12 - rockchip,grf : phandle to the syscon managing the "general
13 register files" - phy should be a child of the GRF instead
15 Sub-nodes:
16 Each PHY should be represented as a sub-node.
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| /Documentation/devicetree/bindings/dma/ |
| D | mv-xor.txt | 4 - compatible: Should be one of the following:
5 - "marvell,orion-xor"
6 - "marvell,armada-380-xor"
7 - "marvell,armada-3700-xor".
8 - reg: Should contain registers location and length (two sets)
11 - clocks: pointer to the reference clock
13 The DT node must also contains sub-nodes for each XOR channel that the
14 XOR engine has. Those sub-nodes have the following required
16 - interrupts: interrupt of the XOR channel
18 The sub-nodes used to contain one or several of the following
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| D | adi,axi-dmac.txt | 1 Analog Device AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
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| /Documentation/devicetree/bindings/bus/ |
| D | omap-ocp2scp.txt | 1 * OMAP OCP2SCP - ocp interface to scp interface
4 - compatible : Should be "ti,am437x-ocp2scp" for AM437x processor
5 Should be "ti,omap-ocp2scp" for all others
6 - reg : Address and length of the register set for the device
7 - #address-cells, #size-cells : Must be present if the device has sub-nodes
8 - ranges : the child address space are mapped 1:1 onto the parent address space
9 - ti,hwmods : must be "ocp2scp_usb_phy"
11 Sub-nodes:
12 All the devices connected to ocp2scp are described using sub-node to ocp2scp
15 compatible = "ti,omap-ocp2scp";
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| /Documentation/devicetree/bindings/mtd/ |
| D | denali-nand.txt | 4 - compatible : should be one of the following:
5 "altr,socfpga-denali-nand" - for Altera SOCFPGA
6 "socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a)
7 "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b)
8 - reg : should contain registers location and length for data and reg.
9 - reg-names: Should contain the reg names "nand_data" and "denali_reg"
10 - #address-cells: should be 1. The cell encodes the chip select connection.
11 - #size-cells : should be 0.
12 - interrupts : The interrupt number.
13 - clocks: should contain phandle of the controller core clock, the bus
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| D | samsung-s3c2410.txt | 4 - compatible : The possible values are:
5 "samsung,s3c2410-nand"
6 "samsung,s3c2412-nand"
7 "samsung,s3c2440-nand"
8 - reg : register's location and length.
9 - #address-cells, #size-cells : see nand-controller.yaml
10 - clocks : phandle to the nand controller clock
11 - clock-names : must contain "nand"
13 Optional child nodes:
14 Child nodes representing the available nand chips.
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| /Documentation/devicetree/bindings/ata/ |
| D | ahci-platform.txt | 3 SATA nodes are defined to describe on-chip Serial ATA controllers.
6 It is possible, but not required, to represent each port as a sub-node.
11 - compatible : compatible string, one of:
12 - "allwinner,sun4i-a10-ahci"
13 - "allwinner,sun8i-r40-ahci"
14 - "brcm,iproc-ahci"
15 - "hisilicon,hisi-ahci"
16 - "cavium,octeon-7130-ahci"
17 - "ibm,476gtr-ahci"
18 - "marvell,armada-380-ahci"
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| /Documentation/media/uapi/v4l/ |
| D | pixfmt-tch-td08.rst | 4 .. Foundation, with no Invariant Sections, no Front-Cover Texts
5 .. and no Back-Cover Texts. A copy of the license is included at
6 .. Documentation/media/uapi/fdl-appendix.rst.
8 .. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections
10 .. _V4L2-TCH-FMT-DELTA-TD08:
18 8-bit signed Touch Delta
25 Delta values may range from -128 to 127. Typically the values will vary through
27 may be seen if one of the touchscreen nodes has a fault or the line is not
35 .. flat-table::
36 :header-rows: 0
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| D | pixfmt-tch-td16.rst | 4 .. Foundation, with no Invariant Sections, no Front-Cover Texts
5 .. and no Back-Cover Texts. A copy of the license is included at
6 .. Documentation/media/uapi/fdl-appendix.rst.
8 .. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections
10 .. _V4L2-TCH-FMT-DELTA-TD16:
18 16-bit signed Touch Delta
26 Delta values may range from -32768 to 32767. Typically the values will vary
28 full value may be seen if one of the touchscreen nodes has a fault or the line
34 .. flat-table::
35 :header-rows: 0
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| /Documentation/devicetree/bindings/pci/ |
| D | ralink,rt3883-pci.txt | 7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
26 2) Child nodes
28 The main node must have two child nodes which describes the built-in
35 - interrupt-controller: identifies the node as an interrupt controller
37 - #address-cells: specifies the number of cells needed to encode an
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| /Documentation/devicetree/bindings/misc/ |
| D | fsl,qoriq-mc.txt | 3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
33 - compatible
35 Definition: Must be "fsl,qoriq-mc". A Freescale Management Complex
40 - reg
41 Value type: <prop-encoded-array>
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| /Documentation/media/v4l-drivers/ |
| D | fimc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 Copyright |copy| 2012 - 2013 Samsung Electronics Co., Ltd.
17 drivers/media/platform/exynos4-is directory.
20 --------------
22 S5PC100 (mem-to-mem only), S5PV210, EXYNOS4210
25 ------------------
27 - camera parallel interface capture (ITU-R.BT601/565);
28 - camera serial interface capture (MIPI-CSI2);
29 - memory-to-memory processing (color space conversion, scaling, mirror
31 - dynamic pipeline re-configuration at runtime (re-attachment of any FIMC
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | raideng.txt | 1 * Freescale 85xx RAID Engine nodes
3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
11 - compatible: Should contain "fsl,raideng-v1.0" as the value
15 - reg: offset and length of the register set for the device
16 - ranges: standard ranges property specifying the translation
22 compatible = "fsl,raideng-v1.0";
23 #address-cells = <1>;
24 #size-cells = <1>;
30 There must be a sub-node for each job queue present in RAID Engine
31 This node must be a sub-node of the main RAID Engine node
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| /Documentation/devicetree/bindings/sram/ |
| D | samsung-sram.txt | 2 ------------------------------------
4 Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
8 Therefore reserved section sub-nodes have to be added to the mmio-sram
9 declaration. These nodes are of two types depending upon secure or
10 non-secure execution environment.
12 Required sub-node properties:
13 - compatible : depending upon boot mode, should be
14 "samsung,exynos4210-sysram" : for Secure SYSRAM
15 "samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM
17 The rest of the properties should follow the generic mmio-sram discription
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