Searched +full:timebase +full:- +full:frequency (Results 1 – 3 of 3) sorted by relevance
1 Xilinx AXI/PLB soft-core watchdog Device Tree Bindings2 ---------------------------------------------------------5 - compatible : Should be "xlnx,xps-timebase-wdt-1.00.a" or6 "xlnx,xps-timebase-wdt-1.01.a".7 - reg : Physical base address and size10 - clocks : Input clock specifier. Refer to common clock12 - clock-frequency : Frequency of clock in Hz13 - xlnx,wdt-enable-once : 0 - Watchdog can be restarted14 1 - Watchdog can be enabled just once15 - xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles,[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: RISC-V bindings for 'cpus' DT nodes10 - Paul Walmsley <paul.walmsley@sifive.com>11 - Palmer Dabbelt <palmer@sifive.com>14 This document uses some terminology common to the RISC-V community18 mandated by the RISC-V ISA: a PC and some registers. This28 - items:29 - enum:[all …]
2 --------------------------------------------------7 Freescale Semiconductor, FSL SOC and 32-bit additions14 I - Introduction21 II - The DT block format27 III - Required content of the device tree40 IV - "dtc", the device tree compiler42 V - Recommendations for a bootloader44 VI - System-on-a-chip devices and nodes48 VII - Specifying interrupt information for devices50 2) interrupt-parent property[all …]