| /Documentation/devicetree/bindings/timer/ |
| D | rockchip,rk-timer.txt | 1 Rockchip rk timer
5 "rockchip,rv1108-timer", "rockchip,rk3288-timer": for Rockchip RV1108
6 "rockchip,rk3036-timer", "rockchip,rk3288-timer": for Rockchip RK3036
7 "rockchip,rk3066-timer", "rockchip,rk3288-timer": for Rockchip RK3066
8 "rockchip,rk3188-timer", "rockchip,rk3288-timer": for Rockchip RK3188
9 "rockchip,rk3228-timer", "rockchip,rk3288-timer": for Rockchip RK3228
10 "rockchip,rk3229-timer", "rockchip,rk3288-timer": for Rockchip RK3229
11 "rockchip,rk3288-timer": for Rockchip RK3288
12 "rockchip,rk3368-timer", "rockchip,rk3288-timer": for Rockchip RK3368
13 "rockchip,rk3399-timer": for Rockchip RK3399
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| D | ti,timer.txt | 1 OMAP Timer bindings
5 OMAP44xx devices have timer instances that are 100%
8 So for OMAP44xx devices timer instances may use
11 ti,omap2420-timer (applicable to OMAP24xx devices)
12 ti,omap3430-timer (applicable to OMAP3xxx/44xx devices)
13 ti,omap4430-timer (applicable to OMAP44xx devices)
14 ti,omap5430-timer (applicable to OMAP543x devices)
15 ti,am335x-timer (applicable to AM335x devices)
16 ti,am335x-timer-1ms (applicable to AM335x devices)
18 - reg: Contains timer register address range (base address and
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| D | mediatek,mtk-timer.txt | 5 - GPT (General Purpose Timer)
6 - SYST (System Timer)
8 The proper timer will be selected automatically by driver.
13 * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT)
14 * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT)
15 * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT)
16 * "mediatek,mt7623-timer" for MT7623 compatible timers (GPT)
17 * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
18 * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
19 * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
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| D | faraday,fttmr010.txt | 1 Faraday Technology timer
3 This timer is a generic IP block from Faraday Technology, embedded in the
10 "cortina,gemini-timer", "faraday,fttmr010"
11 "moxa,moxart-timer", "faraday,fttmr010"
12 "aspeed,ast2400-timer"
13 "aspeed,ast2500-timer"
16 - interrupts : Should contain the three timer interrupts usually with
22 - clock-names : should be "EXTCLK" and "PCLK" for the external tick timer
25 type is "cortina,gemini-timer"
29 timer@43000000 {
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| D | cirrus,clps711x-timer.txt | 1 * Cirrus Logic CLPS711X Timer Counter
4 - compatible: Shall contain "cirrus,ep7209-timer".
6 - interrupts: The interrupt number of the timer.
7 - clocks : phandle of timer reference clock.
9 Note: Each timer should have an alias correctly numbered in "aliases" node.
17 timer1: timer@80000300 {
18 compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
24 timer2: timer@80000340 {
25 compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
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| D | qcom,msm-timer.txt | 1 * MSM Timer
5 - compatible : Should at least contain "qcom,msm-timer". More specific
8 "qcom,kpss-timer" - krait subsystem
9 "qcom,scss-timer" - scorpion subsystem
11 - interrupts : Interrupts for the debug timer, the first general purpose
12 timer, and optionally a second general purpose timer, and
15 - reg : Specifies the base address of the timer registers.
23 - clock-frequency : The frequency of the debug timer and the general purpose
24 timer(s) in Hz in that order.
28 - cpu-offset : per-cpu offset used when the timer is accessed without the
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| D | arm,arch_timer.yaml | 4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
7 title: ARM architected timer
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
15 physical and optional virtual timer per frame.
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
26 - arm,cortex-a15-timer
28 - arm,armv7-timer
31 - arm,armv7-timer
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| D | lsi,zevio-timer.txt | 1 TI-NSPIRE timer
5 - compatible : should be "lsi,zevio-timer".
6 - reg : The physical base address and size of the timer (always first).
11 - interrupts : The interrupt number of the first timer.
13 (always after timer base address)
15 If any of the optional properties are not given, the timer is added as a
20 timer {
21 compatible = "lsi,zevio-timer";
29 timer {
30 compatible = "lsi,zevio-timer";
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| D | nuvoton,npcm7xx-timer.txt | 1 Nuvoton NPCM7xx timer
3 Nuvoton NPCM7xx have three timer modules, each timer module provides five 24-bit
4 timer counters.
7 - compatible : "nuvoton,npcm750-timer" for Poleg NPCM750.
9 - interrupts : Contain the timer interrupt with flags for
11 - clocks : phandle of timer reference clock (usually a 25 MHz clock).
15 timer@f0008000 {
16 compatible = "nuvoton,npcm750-timer";
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| D | marvell,armada-370-xp-timer.txt | 6 "marvell,armada-370-timer",
7 "marvell,armada-375-timer",
8 "marvell,armada-xp-timer".
9 - interrupts: Should contain the list of Global Timer interrupts and
10 then local timer interrupts
12 pair for the Global Timer registers, second pair for the
15 Clocks required for compatible = "marvell,armada-370-timer":
18 Clocks required for compatibles = "marvell,armada-xp-timer",
19 "marvell,armada-375-timer":
29 timer {
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| D | allwinner,sun4i-a10-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/allwinner,sun4i-a10-timer.yaml#
7 title: Allwinner A10 Timer Device Tree Bindings
16 - allwinner,sun4i-a10-timer
17 - allwinner,sun8i-a23-timer
18 - allwinner,sun8i-v3s-timer
19 - allwinner,suniv-f1c100s-timer
36 const: allwinner,sun4i-a10-timer
48 const: allwinner,sun8i-a23-timer
60 const: allwinner,sun8i-v3s-timer
72 const: allwinner,suniv-f1c100s-timer
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| D | ti,keystone-timer.txt | 1 * Device tree bindings for Texas instruments Keystone timer
3 This document provides bindings for the 64-bit timer in the KeyStone
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 It is global timer is a free running up-counter and can generate interrupt
17 - compatible : should be "ti,keystone-timer".
19 - interrupts : interrupt generated by the timer.
20 - clocks : the clock feeding the timer clock.
24 timer@22f0000 {
25 compatible = "ti,keystone-timer";
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| D | arm,mps2-timer.txt | 1 ARM MPS2 timer
6 - compatible : Should be "arm,mps2-timer"
8 - interrupts : Reference to the timer interrupt
11 - clocks : The input clock of the timer
12 - clock-frequency : The rate in HZ in input of the ARM MPS2 timer
16 timer1: mps2-timer@40000000 {
17 compatible = "arm,mps2-timer";
23 timer2: mps2-timer@40001000 {
24 compatible = "arm,mps2-timer";
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| D | nvidia,tegra30-timer.txt | 1 NVIDIA Tegra30 timer
3 The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
9 - compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise,
10 must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where
13 - interrupts : A list of 6 interrupts; one per each of timer channels 1
18 timer {
19 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
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| D | samsung,exynos4210-mct.txt | 1 Samsung's Multi Core Timer (MCT)
3 The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
4 global timer and CPU local timers. The global timer is a 64-bit free running
8 one CPU local timer instantiated in MCT for every CPU in the system.
20 should be the order of the interrupts specified. The local timer interrupts
21 should be specified after the four global timer interrupts have been
24 0: Global Timer Interrupt 0
25 1: Global Timer Interrupt 1
26 2: Global Timer Interrupt 2
27 3: Global Timer Interrupt 3
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| D | arm,twd.txt | 1 * ARM Timer Watchdog
4 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
10 ** Timer node required properties:
13 "arm,cortex-a9-twd-timer"
14 "arm,cortex-a5-twd-timer"
15 "arm,arm11mp-twd-timer"
19 - reg : Specify the base address and the size of the TWD timer
24 - always-on : a boolean property. If present, the timer is powered through
29 twd-timer@2c000600 {
30 compatible = "arm,arm11mp-twd-timer"";
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| D | renesas,16bit-timer.txt | 1 * Renesas H8/300 16bit timer
3 The 16bit timer is a 16bit timer/counter with configurable clock inputs and
8 - compatible: must contain "renesas,16bit-timer"
9 - reg: base address and length of the registers block for the timer module.
10 - interrupts: interrupt-specifier for the timer, IMIA
13 - renesas,channel: timer channel number.
17 timer16: timer@ffff68 {
18 compatible = "reneas,16bit-timer";
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| D | st,spear-timer.txt | 1 * SPEAr ARM Timer
3 ** Timer node required properties:
6 "st,spear-timer"
7 - reg: Address range of the timer registers
8 - interrupt: Should contain the timer interrupt number
12 timer@f0000000 {
13 compatible = "st,spear-timer";
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| D | renesas,8bit-timer.txt | 1 * Renesas H8/300 8bit timer
3 The 8bit timer is a 8bit timer/counter with configurable clock inputs and
10 - compatible: must contain "renesas,8bit-timer"
11 - reg: base address and length of the registers block for the timer module.
12 - interrupts: interrupt-specifier for the timer, CMIA and TOVI
18 timer8_0: timer@ffff80 {
19 compatible = "renesas,8bit-timer";
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| D | ti,davinci-timer.txt | 1 * Device tree bindings for Texas Instruments DaVinci timer
3 This document provides bindings for the 64-bit timer in the DaVinci
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 The timer is a free running up-counter and can generate interrupts when the
17 - compatible : should be "ti,da830-timer".
19 - interrupts : interrupts generated by the timer.
24 - clocks : the clock feeding the timer clock.
28 clocksource: timer@20000 {
29 compatible = "ti,da830-timer";
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| D | arm,sp804.txt | 6 - interrupts: Should contain the list of Dual Timer interrupts. This is the
7 interrupt for timer 1 and timer 2. In the case of a single entry, it is
9 specifies which timer interrupt is connected.
10 - reg: Should contain location and length for dual timer register.
11 - clocks: clocks driving the dual timer hardware. This list should be 1 or 3
17 - arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this
18 specifies if the irq connection is for timer 1 or timer 2. A value of 1
23 timer0: timer@fc800000 {
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-platform-ACPI-TAD | 15 BIT(5): The AC timer wakes up from S4 if set
16 BIT(6): The AC timer wakes up from S5 if set
17 BIT(7): The DC timer wakes up from S4 if set
18 BIT(8): The DC timer wakes up from S5 if set
26 (RW) The AC alarm timer value.
28 Reads return the current AC alarm timer value in seconds or
31 Write a new AC alarm timer value in seconds or "disabled" to it
32 to set the AC alarm timer or to disable it, respectively.
34 If the AC alarm timer is set through this attribute and it
43 (RW) The AC alarm expired timer wake policy (see ACPI 6.2,
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic-timer.txt | 4 - compatible: "fsl,mpic-global-timer"
6 - reg : Contains two regions. The first is the main timer register bank
7 (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control
11 timer interrupts can be used. This property is optional; without this,
14 - interrupts: one interrupt per timer in the group, in order, starting
15 with timer zero. If timer-available-ranges is present, only the
20 timer0: timer@41100 {
21 compatible = "fsl,mpic-global-timer";
31 timer1: timer@42100 {
32 compatible = "fsl,mpic-global-timer";
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| /Documentation/devicetree/bindings/rtc/ |
| D | dw-apb.txt | 1 * Designware APB timer
5 "snps,dw-apb-timer"
6 "snps,dw-apb-timer-sp" <DEPRECATED>
7 "snps,dw-apb-timer-osc" <DEPRECATED>
10 - interrupts: IRQ line for the timer.
16 - clock-names : should contain "timer" and "pclk" entries, matching entries
18 - clock-frequency: The frequency in HZ of the timer.
26 timer@ffe00000 {
27 compatible = "snps,dw-apb-timer";
31 clock-names = "timer", "pclk";
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| /Documentation/leds/ |
| D | ledtrig-transient.rst | 5 The leds timer trigger does not currently have an interface to activate
6 a one shot timer. The current support allows for setting two timers, one for
15 Without one shot timer interface, user space can still use timer trigger to
16 set a timer to hold a state, however when user space application crashes or
17 goes away without deactivating the timer, the hardware will be left in that
22 PMIC. There is a need to activate one shot timer to control the vibrate
26 Transient trigger addresses the need for one shot timer activation. The
60 deactivation routine, will cancel any timer that is active before it cleans
77 - duration allows setting timer value in msecs. The initial value is 0.
78 - activate allows activating and deactivating the timer specified by
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