Searched full:timers (Results 1 – 25 of 94) sorted by relevance
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| /Documentation/devicetree/bindings/timer/ |
| D | mediatek,mtk-timer.txt | 1 MediaTek Timers
4 MediaTek SoCs have two different timers on different platforms,
13 * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT)
14 * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT)
15 * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT)
16 * "mediatek,mt7623-timer" for MT7623 compatible timers (GPT)
17 * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
18 * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
19 * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
20 * "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
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| D | ti,davinci-timer.txt | 5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
6 timers, each half can operate in conjunction (chain mode) or independently
12 Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
13 watchdog timers.
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| D | andestech,atcpit100-timer.txt | 6 This timer is a set of compact multi-function timers, which can be
7 used as pulse width modulators (PWM) as well as simple timers.
12 Two 16-bit timers
13 Four 8-bit timers
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| D | spreadtrum,sprd-timer.txt | 1 Spreadtrum timers
3 The Spreadtrum SC9860 platform provides 3 general-purpose timers.
4 These timers can support 32bit or 64bit counter, as well as supporting
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| D | samsung,exynos4210-mct.txt | 4 global timer and CPU local timers. The global timer is a 64-bit free running
6 four preset counter values. The CPU local timers are 32-bit free running
34 For MCT block that uses a per-processor interrupt for local timers, such
36 interrupt might be specified, meaning that all local timers use the same
39 Example 1: In this example, the IP contains two local timers, using separate
73 Example 3: In this example, the IP contains four local timers, but using
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| D | marvell,armada-370-xp-timer.txt | 1 Marvell Armada 370 and Armada XP Timers
11 - reg: Should contain location and length for timers register. First
13 local/private timers.
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| D | ti,keystone-timer.txt | 5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
6 timers, each half can operate in conjunction (chain mode) or independently
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| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-samsung.txt | 1 * Samsung PWM timers
4 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
12 samsung,s3c2410-pwm - for 16-bit timers present on S3C24xx SoCs
13 samsung,s3c6400-pwm - for 32-bit timers present on S3C64xx SoCs
14 samsung,s5p6440-pwm - for 32-bit timers present on S5P64x0 SoCs
15 samsung,s5pc100-pwm - for 32-bit timers present on S5PC100, S5PV210,
17 samsung,exynos4210-pwm - for 32-bit timers present on Exynos4210,
23 - "timers" - PWM base clock used to generate PWM signals,
48 clock-names = "timers";
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| D | pwm-omap-dmtimer.txt | 1 * OMAP PWM for dual-mode timers
5 - ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer.txt for info
6 about these timers.
11 - ti,prescaler: Should be a value between 0 and 7, see the timers datasheet
20 ti,timers = <&timer9>;
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| D | pwm-stm32.txt | 1 STMicroelectronics STM32 Timers PWM bindings
3 Must be a sub-node of an STM32 Timers device tree node.
4 See ../mfd/stm32-timers.txt for details about the parent node.
23 timers@40010000 {
26 compatible = "st,stm32-timers";
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| /Documentation/devicetree/bindings/iio/timer/ |
| D | stm32-timer-trigger.txt | 1 STMicroelectronics STM32 Timers IIO timer bindings
3 Must be a sub-node of an STM32 Timers device tree node.
4 See ../mfd/stm32-timers.txt for details about the parent node.
13 timers@40010000 {
16 compatible = "st,stm32-timers";
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| /Documentation/timers/ |
| D | hrtimers.rst | 2 hrtimers - subsystem for high-resolution kernel timers
5 This patch introduces a new subsystem for high-resolution kernel timers.
8 (kernel/timers.c), why do we need two timer subsystems? After a lot of
18 - the forced handling of low-resolution and high-resolution timers in
20 mess. The timers.c code is very "tightly coded" around jiffies and
27 high-res timers.
30 necessitate a more complex handling of high resolution timers, which
34 degrading other portions of the timers.c code in an unacceptable way.
38 the required readjusting of absolute CLOCK_REALTIME timers at
41 timers.
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| D | hpet.rst | 12 also called "timers", which can be misleading since usually timers are
19 mode where the first two comparators block interrupts from 8254 timers
30 file:samples/timers/hpet_example.c
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| D | index.rst | 4 timers title
15 timers-howto
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| D | highres.rst | 2 High resolution timers and dynamic ticks design notes
34 the base implementation are covered in Documentation/timers/hrtimers.rst. See
38 timers are:
64 Timers" was written by J. Stultz, D.V. Hart, & N. Aravamudan.
82 functionality like high resolution timers or dynamic ticks.
102 accounting, profiling, and high resolution timers.
134 enabling of high resolution timers and dynamic ticks is simply provided by
156 configured for high resolution timers can run on a system which lacks the
167 The time ordered insertion of timers provides all the infrastructure to decide
175 from the clock event distribution code and moves expired timers from the
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| /Documentation/devicetree/bindings/mfd/ |
| D | stm32-timers.txt | 1 STM32 Timers driver bindings
4 - advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable
6 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a
8 - basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
11 - compatible: must be "st,stm32-timers"
34 timers@40010000 {
37 compatible = "st,stm32-timers";
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| /Documentation/devicetree/bindings/mips/brcm/ |
| D | soc.txt | 145 == Timers
148 timers that can be used.
153 "brcm,bcm7425-timers"
154 "brcm,bcm7429-timers"
155 "brcm,bcm7435-timers" and
156 "brcm,brcmstb-timers"
157 - reg : the timers register range
162 timers: timer@4067c0 {
163 compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers";
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic-timer.txt | 1 * Freescale MPIC timers
12 all timers within the group can be used.
16 interrupts that correspond to available timers shall be present.
24 /* Another AMP partition is using timers 0 and 1 */
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| /Documentation/devicetree/bindings/counter/ |
| D | stm32-timer-cnt.txt | 8 See ../mfd/stm32-timers.txt for details about the parent node.
18 timers@40010000 {
21 compatible = "st,stm32-timers";
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| /Documentation/devicetree/bindings/arm/ |
| D | picoxcell.txt | 11 Timers required properties:
17 Note: two timers are required - one for the scheduler clock and one for the
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| /Documentation/devicetree/bindings/x86/ |
| D | timer.txt | 1 Timers
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| /Documentation/devicetree/bindings/input/ |
| D | pwm-vibrator.txt | 45 ti,timers = <&timer8>;
55 ti,timers = <&timer9>;
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| /Documentation/devicetree/bindings/watchdog/ |
| D | mt7621-wdt.txt | 1 Ralink Watchdog Timers
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| D | rt2880-wdt.txt | 1 Ralink Watchdog Timers
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | mips-gic.txt | 6 global timer, per-CPU count/compare timers, and a watchdog.
39 - clock-frequency : Clock frequency at which the GIC timers operate.
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