Searched +full:tlb +full:- +full:split (Results 1 – 7 of 7) sorted by relevance
| /Documentation/admin-guide/mm/ |
| D | transhuge.rst | 28 requiring larger clear-page copy-page in page faults which is a
38 1) the TLB miss will run faster (especially with virtualization using
42 2) a single TLB entry will be mapping a much larger amount of virtual
43 memory in turn reducing the number of TLB misses. With
44 virtualization and nested pagetables the TLB can be mapped of
47 the two is using hugepages just because of the fact the TLB miss is
78 possible to disable hugepages system-wide and to only have them inside
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149 should be self-explanatory.
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| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
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| /Documentation/admin-guide/hw-vuln/ |
| D | multihit.rst | 6 instruction fetch hits multiple entries in the instruction TLB. This can
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18 - non-Intel processors
20 - Some Atoms (Airmont, Bonnell, Goldmont, GoldmontPlus, Saltwell, Silvermont)
22 - Intel processors that have the PSCHANGE_MC_NO bit set in the
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32 CVE-2018-12207 Machine Check Error Avoidance on Page Size Change
37 -------
42 the illusion of a very large memory for processors. This virtual space is split
47 processors include a structure, called TLB, that caches recent translations.
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| /Documentation/core-api/ |
| D | cachetlb.rst | 2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
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| /Documentation/vm/ |
| D | highmem.rst | 25 VM space so that we don't have to pay the full TLB invalidation costs for
29 The traditional split for architectures using this approach is 3:1, 3GiB for
32 +--------+ 0xffffffff
34 +--------+ 0xc0000000
38 +--------+ 0x00000000
41 time, but because we need virtual address space for other things - including
42 temporary maps to access the rest of the physical memory - the actual direct
114 manipulate the kernel's page tables, the data TLB and/or the MMU's registers.
129 of RAM into your 32-bit machine. This has a number of consequences:
131 * Linux needs a page-frame structure for each page in the system and the
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| D | hmm.rst | 7 Provide infrastructure and helpers to integrate non-conventional memory (device
23 CPU page-table mirroring works and the purpose of HMM in this context. The
37 regular file backed memory). From here on I will refer to this aspect as split
42 Split address space happens because devices can only access memory allocated
54 complex data set needs to re-map all the pointer relations between each of its
58 Split address space also means that libraries cannot transparently use data
71 are only do-able with a shared address space. It is also more reasonable to use
97 two-way cache coherency between CPU and device and allow all atomic operations the
117 allocate a buffer (or use a pool of pre-allocated buffers) and write GPU
159 /* release() - release hmm_mirror
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| /Documentation/RCU/ |
| D | RTFP.txt | 4 This document describes RCU-related publications, and is followed by
19 with short-lived threads, such as the K42 research operating system.
20 However, Linux has long-lived tasks, so more is needed.
23 serialization, which is an RCU-like mechanism that relies on the presence
27 that these overheads were not so expensive in the mid-80s. Nonetheless,
28 passive serialization appears to be the first deferred-destruction
30 has lapsed, so this approach may be used in non-GPL software, if desired.
34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].
36 this paper helped inspire the update-side batching used in the later
38 a description of Argus that noted that use of out-of-date values can
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