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| /Documentation/devicetree/bindings/sound/ |
| D | img,pistachio-internal-dac.txt | 5 - compatible: "img,pistachio-internal-dac"
7 - img,cr-top : Must contain a phandle to the top level control syscon
10 - VDD-supply : Digital power supply regulator (+1.8V or +3.3V)
14 internal_dac: internal-dac {
15 compatible = "img,pistachio-internal-dac";
16 img,cr-top = <&cr_top>;
17 VDD-supply = <&supply3v3>;
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| /Documentation/devicetree/bindings/clock/ |
| D | pistachio-clock.txt | 5 general control, and top general control) which are instantiated individually
6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
21 co-processor), audio, and several peripherals.
24 - compatible: Must be "img,pistachio-clk".
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| D | zx296702-clk.txt | 5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "zte,zx296702-topcrm-clk":
10 zx296702 top clock selection, divider and gating
12 "zte,zx296702-lsp0crpm-clk" and
13 "zte,zx296702-lsp1crpm-clk":
14 zx296702 device level clock selection and gating
16 - reg: Address and length of the register set
19 ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h
24 compatible = "zte,zx296702-topcrm-clk";
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| D | zx296718-clk.txt | 5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "zte,zx296718-topcrm":
10 zx296718 top clock selection, divider and gating
12 "zte,zx296718-lsp0crm" and
13 "zte,zx296718-lsp1crm":
14 zx296718 device level clock selection and gating
16 "zte,zx296718-audiocrm":
19 - reg: Address and length of the register set
22 ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h
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| /Documentation/media/v4l-drivers/ |
| D | pvrusb2.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 ----------
13 Its history started with the reverse-engineering effort by Björn
29 1. Low level wire-protocol implementation with the device.
34 3. High level hardware driver implementation which coordinates all
38 tear-down, arbitration, and interaction with high level
42 5. High level interfaces which glue the driver to various published
45 The most important shearing layer is between the top 2 layers. A
47 conceivable API can be laid on top of the core driver. (Yes, the
54 right now the V4L high level interface is the most complete, the
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| /Documentation/devicetree/bindings/opp/ |
| D | qcom-opp.txt | 3 The bindings are based on top of the operating-points-v2 bindings
10 - compatible: Allow OPPs to express their compatibility. It should be:
11 "operating-points-v2-qcom-level"
16 - qcom,opp-fuse-level: A positive value representing the fuse corner/level
18 a certain fuse corner/level. A fuse corner/level contains e.g. ref uV,
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,bcm2835-armctrl-ic.txt | 1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
9 interrupts, but the per-CPU interrupt controller is the root, and an
14 - compatible : should be "brcm,bcm2835-armctrl-ic" or
15 "brcm,bcm2836-armctrl-ic"
16 - reg : Specifies base physical address and size of the registers.
17 - interrupt-controller : Identifies the node as an interrupt controller
18 - #interrupt-cells : Specifies the number of cells needed to encode an
28 Additional required properties for brcm,bcm2836-armctrl-ic:
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| D | brcm,bcm7038-l1-intc.txt | 1 Broadcom BCM7038-style Level 1 interrupt controller
3 This block is a first level interrupt controller that is typically connected
4 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
9 - 64, 96, 128, or 160 incoming level IRQ lines
11 - Most onchip peripherals are wired directly to an L1 input
13 - A separate instance of the register set for each CPU, allowing individual
16 - Atomic mask/unmask operations
18 - No polarity/level/edge settings
20 - No FIFO or priority encoder logic; software is expected to read all
21 2-5 status words to determine which IRQs are pending
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| D | abilis,tb10x-ictl.txt | 1 TB10x Top Level Interrupt Controller
5 one-to-one mapping of external interrupt sources to CPU interrupts and
9 -------------------
11 - compatible: Should be "abilis,tb10x-ictl"
12 - reg: specifies physical base address and size of register range.
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
16 - interrupts: Specifies the list of interrupt lines which are handled by
18 are mapped one-to-one to parent interrupts.
21 -------
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| /Documentation/admin-guide/cifs/ |
| D | winucase_convert.pl | 1 #!/usr/bin/perl -w
3 # winucase_convert.pl -- convert "Windows 8 Upper Case Mapping Table.txt" to
4 # a two-level set of C arrays.
28 $top[$firstchar][$secondchar] = $uppercase;
32 next if (!$top[$i]);
41 printf("0x%4.4x,", $top[$i][$j] ? $top[$i][$j] : 0);
50 } elsif ($top[$i]) {
56 if ($top[$i]) {
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| /Documentation/devicetree/bindings/ |
| D | jailhouse.txt | 1 Jailhouse non-root cell device tree bindings
2 --------------------------------------------
4 When running in a non-root Jailhouse cell (partition), the device tree of this
5 platform shall have a top-level "hypervisor" node with the following
8 - compatible = "jailhouse,cell"
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| /Documentation/devicetree/bindings/mfd/ |
| D | cros-ec.txt | 3 Google's ChromeOS EC is a Cortex-M device which talks to the AP and
8 its own driver which connects to the top level interface-agnostic EC driver.
9 Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to
10 the top-level driver.
13 - compatible: "google,cros-ec-i2c"
14 - reg: I2C slave address
17 - compatible: "google,cros-ec-spi"
18 - reg: SPI chip select
21 - compatible: "google,cros-ec-rpmsg"
24 - google,cros-ec-spi-pre-delay: Some implementations of the EC need a little
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| D | max77650.txt | 1 MAX77650 ultra low-power PMIC from Maxim Integrated.
4 -------------------
5 - compatible: Must be "maxim,max77650"
6 - reg: I2C device address.
7 - interrupts: The interrupt on the parent the controller is
9 - interrupt-controller: Marks the device node as an interrupt controller.
10 - #interrupt-cells: Must be <2>.
12 - gpio-controller: Marks the device node as a gpio controller.
13 - #gpio-cells: Must be <2>. The first cell is the pin number and
18 --------------------
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| /Documentation/devicetree/bindings/gpio/ |
| D | mediatek,mt7621-gpio.txt | 6 interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU
9 Required properties for the top level node:
10 - #gpio-cells : Should be two. The first cell is the GPIO pin number and the
11 second cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
13 - #interrupt-cells : Specifies the number of cells needed to encode an
16 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
17 - compatible:
18 - "mediatek,mt7621-gpio" for Mediatek controllers
19 - reg : Physical base address and length of the controller's registers
20 - interrupt-parent : phandle of the parent interrupt controller.
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| /Documentation/driver-api/fpga/ |
| D | intro.rst | 16 other users. Write the linux-fpga mailing list and maintainers and
24 ------------
27 this is the subsystem for you. Low level FPGA manager drivers contain
29 includes the framework in fpga-mgr.c and the low level drivers that
33 -----------
37 programming begins and re-enabled afterwards. An FPGA bridge may be
40 of an FPGA. This subsystem includes fpga-bridge.c and the low level
44 -----------
46 If you are adding a new interface to the FPGA framework, add it on top
49 The FPGA Region framework (fpga-region.c) associates managers and
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| /Documentation/devicetree/bindings/fsi/ |
| D | fsi.txt | 4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
32 fsi-slave-engine@<addr> {
39 Note that since the bus is probe-able, some (or all) of the topology may
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| /Documentation/x86/ |
| D | pti.rst | 1 .. SPDX-License-Identifier: GPL-2.0
27 This approach helps to ensure that side-channel attacks leveraging
30 Once enabled at compile-time, it can be disabled at boot with the
31 'nopti' or 'pti=' kernel parameters (see kernel-parameters.txt).
42 crippled by setting the NX bit in the top level. This ensures
43 that any missed kernel->user CR3 switch will immediately crash
49 each CPU's copy of the area a compile-time-fixed virtual address.
53 makes entries in the top (PGD) level. In addition to setting the
57 This sharing at the PGD level also inherently shares all the lower
65 Protection against side-channel attacks is important. But,
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| /Documentation/ABI/testing/ |
| D | sysfs-class-led | 8 non-zero brightness settings. The value is between 0 and
13 Writing non-zero to this file while trigger is active changes the
14 top brightness trigger is going to use.
21 Maximum brightness level for this LED, default is 255 (LED_FULL).
30 Last hardware set brightness level for this LED. Some LEDs
38 Reading this file will return the last brightness level set
53 their documentation see sysfs-class-led-trigger-*.
|
| /Documentation/admin-guide/mm/ |
| D | concepts.rst | 9 systems from MMU-less microcontrollers to supercomputers. The memory
54 The tables at the lowest level of the hierarchy contain physical
57 levels. The pointer to the top level page table resides in a
59 register to access the top level page table. The high bits of the
60 virtual address are used to index an entry in the top level page
61 table. That entry is then used to access the next level in the
63 that level page table. The lowest bits in the virtual address define
80 and the third level page tables. In Linux such pages are called
82 improves TLB hit-rate and thus improves overall system performance.
89 :ref:`Documentation/admin-guide/mm/hugetlbpage.rst <hugetlbpage>`.
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| /Documentation/x86/x86_64/ |
| D | mm.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Complete virtual memory map with 4-level page tables
12 - Negative addresses such as "-23 TB" are absolute addresses in bytes, counted down
13 from the top of the 64-bit address space. It's easier to understand the layout
14 when seen both in absolute addresses and in distance-from-top notation.
16 For example 0xffffe90000000000 == -23 TB, it's 23 TB lower than the top of the
17 64-bit address space (ffffffffffffffff).
19 Note that as we get closer to the top of the address space, the notation changes
22 - "16M TB" might look weird at first sight, but it's an easier to visualize size
24 It also shows it nicely how incredibly large 64-bit address space is.
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,video.txt | 2 -------------------------------
5 ---------------
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
10 node of the VIPP represents as a top level node of the pipeline and defines
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
26 - direction: should be either "input" or "output" depending on the direction
34 dma-names = "port0", "port1";
37 #address-cells = <1>;
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| /Documentation/devicetree/bindings/bus/ |
| D | brcm,bus-axi.txt | 5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
13 them manually through device tree. Use an interrupt-map to specify the
17 The top-level axi bus may contain children representing attached cores
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
29 #size-cells = <1>;
30 #interrupt-cells = <1>;
31 interrupt-map-mask = <0x000fffff 0xffff>;
32 interrupt-map =
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| /Documentation/ABI/stable/ |
| D | sysfs-firmware-efi-vars | 17 directory has a name of the form "<key>-<vendor guid>"
20 attributes: A read-only text file enumerating the
33 data: A read-only binary file that can be read
65 in the top-level directory and are used for adding and
|
| /Documentation/kbuild/ |
| D | makefiles.rst | 12 --- 3.1 Goal definitions
13 --- 3.2 Built-in object goals - obj-y
14 --- 3.3 Loadable module goals - obj-m
15 --- 3.4 Objects which export symbols
16 --- 3.5 Library file goals - lib-y
17 --- 3.6 Descending down in directories
18 --- 3.7 Compilation flags
19 --- 3.8 Command line dependency
20 --- 3.9 Dependency tracking
21 --- 3.10 Special Rules
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| /Documentation/devicetree/bindings/reset/ |
| D | img,pistachio-reset.txt | 6 control bits found in the Pistachio SoC top level registers.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
25 compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd";
28 clock-names = "sys";
29 #clock-cells = <1>;
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
33 #reset-cells = <1>;
47 spdif_out: spdif-out@18100d00 {
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