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| /Documentation/driver-api/ |
| D | device_connection.rst | 16 two separate devices.
18 Device connections alone do not create a dependency between the two devices.
20 A dependency between the two devices exists only if one of the two endpoint
32 The connection description consists of the names of the two devices with the
34 is needed if there are multiple connections between the two devices.
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| D | edac.rst | 44 controller. Typically, it contains two channels. Two channels at the
49 is calculated using two DIMMs instead of one. Due to that, it is capable
62 The data size accessed by the memory controller is interlaced into two
78 commonly drive two chip-select pins to a memory stick. A single-ranked
85 A double-ranked stick has two chip-select rows which access different
86 sets of memory devices. The two rows cannot be accessed concurrently.
92 A double-sided stick has two chip-select rows which access different sets
93 of memory devices. The two rows cannot be accessed concurrently.
101 set has two chip-select rows and if double-sided sticks are used these
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| D | i2c.rst | 7 some vendors use another name (such as "Two-Wire Interface", TWI) for
8 the same bus. I2C only needs two signals (SCL for clock, SDA for data),
18 structured around two kinds of driver, and two kinds of device. An I2C
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| /Documentation/devicetree/bindings/sound/ |
| D | fsl,audmix.txt | 3 The Audio Mixer is a on-chip functional module that allows mixing of two
4 audio streams into a single audio stream. Audio Mixer has two input serial
5 audio interfaces. These are driven by two Synchronous Audio interface
8 from two interfaces into a single sample. Before mixing, audio samples of
9 two inputs can be attenuated based on configuration. The output of the
20 Mixing operation is independent of audio sample rate but the two audio
37 DAIs. The current implementation requires two phandles
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| D | cs35l32.txt | 20 of the two: Class G or adaptive LED voltage.
28 Determines the data packed in a two-CS35L32 configuration.
34 - cirrus,sdout-share : SDOUT sharing. Determines whether one or two CS35L32
37 1 = Two IC's.
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| D | madera.txt | 25 For non-muxed inputs the first two cells for that input set the mode for
26 the left and right channel and the second two cells must be 0.
27 For muxed inputs the first two cells for that input set the mode of the
28 left and right A inputs and the second two cells set the mode of the left
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| /Documentation/devicetree/bindings/phy/ |
| D | apm-xgene-phy.txt | 19 Two set of 3-tuple setting for each (up to 3)
25 Two set of 3-tuple setting for each (up to 3)
28 gain control. Two set of 3-tuple setting for each
31 - apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for
35 - apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
39 - apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of
43 - apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of
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| /Documentation/media/uapi/v4l/ |
| D | pixfmt-nv12mt.rst | 17 has two planes - one for luminance and one for chrominance. Chroma
26 This is the two-plane versions of the YUV 4:2:0 format where data is
28 two sub-images or planes. The Y plane has one byte per pixel and pixels
34 alignment is 32. Every four adjacent buffers - two horizontally and two
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio_atmel.txt | 7 - #gpio-cells: Should be two. The first cell is the pin number and
12 - #interrupt-cells: Should be two. The first cell is the pin number and the
13 second cell is used to specify irq type flags, see the two cell description
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| D | gpio-mvebu.txt | 22 for which two entries are expected: one for the general registers,
33 interrupt source. Should be two.
46 - #gpio-cells: Should be two. The first cell is the pin number. The
62 - #pwm-cells: Should be two. The first cell is the GPIO line number. The
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| D | gpio-clps711x.txt | 6 There should be two registers, first is DATA register, the second
9 - #gpio-cells: Should be two. The first cell is the pin number and
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-nxp-fspi.txt | 13 - reg : There are two buses (A and B) with two chip selects each.
20 Example showing the usage of two SPI NOR slave devices on bus A:
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | usb.txt | 5 - reg : the first two cells should contain usb registers location and
6 length, the next two two cells should contain PRAM location and
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| /Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | ifc.txt | 9 - #address-cells : Should be either two or three. The first cell is the
12 - #size-cells : Either one or two, depending on how large each chipselect
15 - interrupts: IFC may have one or two interrupts. If two interrupt
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| /Documentation/devicetree/bindings/mtd/ |
| D | aspeed-smc.txt | 5 three chip selects, two of which are always of SPI type and the third
8 The two SPI flash memory controllers in the AST2500 each support two
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| /Documentation/gpu/ |
| D | komeda-kms.rst | 66 introduces Layer Split, which splits the whole image to two half parts and feeds
67 them to two Layers A and B, and does the scaling independently. After scaling
68 the result need to be fed to merger to merge two part images together, and then
74 compiz result to two parts and then feed them to two scalers.
80 adjusted to fit different usages. And D71 has two pipelines, which support two
84 Two pipelines work independently and separately to drive two display outputs.
87 Two pipelines work together to drive only one display output.
306 capabilities, and a specific component includes two parts:
328 achieve this, split the komeda device into two layers: CORE and CHIP.
384 Layer_Split is quite complicated feature, which splits a big image into two
[all …]
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| /Documentation/devicetree/bindings/leds/backlight/ |
| D | lm3630a-backlight.yaml | 16 controls the current in up to two strings of 10 LEDs per string.
47 The control bank that is used to program the two current sinks. The
48 LM3630A has two control banks (A and B) and are represented as 0 or 1
49 in this property. The two current sinks can be controlled
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| /Documentation/devicetree/bindings/iommu/ |
| D | mediatek,iommu.txt | 4 this M4U have two generations of HW architecture. Generation one uses flat
5 pagetable, and only supports 4K size page mapping. Generation two uses the
60 "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
63 "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
64 "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-iio-adc-max9611 | 15 These attributes describe a single physical component, exposed as two distinct
16 attributes as it is used to calculate two different values: power load and
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| /Documentation/input/devices/ |
| D | elantech.rst | 27 5.2.3 Two finger touch
32 6.2.2 Two finger touch
53 per packet, and provides additional features such as position of two fingers,
55 for 2 fingers the concatenation of two 6 bytes packets) and allows tracking
282 firmware 1.x seem to map one, two and three finger taps
331 tw = 1 when two finger touch
482 Two finger touch
485 Note that the two pairs of coordinates are not exactly the coordinates of the
486 two fingers, but only the pair of the lower-left and upper-right coordinates.
488 defined by these two points.
[all …]
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| D | alps.rst | 66 PSMOUSE_CMD_GETINFO (E9). The first two bytes of the response contains the
75 alps_identify function. For example, there seem to be two hardware init
157 ALPS protocol version 3 has three different packet formats. The first two are
187 usually only appears when there are two or more contacts (although
216 The last two bytes represent a partial bitmap packet, with 3 full packets
309 byte 0: TWO & MULTI L 1 R M 1 Y0-2 Y0-1 Y0-0
314 byte 4: TWO X1-10 TWO X1-9 X1-8 X1-7 X1-6 X1-5 X1-4
315 byte 4: MULTI X1-10 TWO X1-9 X1-8 X1-7 X1-6 Y1-5 1
316 byte 4: NEW X1-10 TWO X1-9 X1-8 X1-7 X1-6 0 0
317 byte 5: TWO & NEW Y1-10 0 Y1-9 Y1-8 Y1-7 Y1-6 Y1-5 Y1-4
[all …]
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| /Documentation/arm64/ |
| D | pointer-authentication.rst | 36 The extension provides five separate keys to generate PACs - two for
37 instruction addresses (APIAKey, APIBKey), two for data addresses
79 bits can vary between the two. Note that the masks apply to TTBR0
94 requesting these two separate cpu features to be enabled. The current KVM
98 if support is added in the future to allow these two features to be
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| /Documentation/admin-guide/device-mapper/ |
| D | unstriped.rst | 85 Intel NVMe drives contain two cores on the physical device.
88 in a 256k stripe across the two cores::
97 neighbor environments. When two partitions are created on the
100 are striped across the two cores. When we unstripe this hardware RAID 0
101 and make partitions on each new exposed device the two partitions are now
121 There will now be two devices that expose Intel NVMe core 0 and 1
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| /Documentation/devicetree/bindings/net/wireless/ |
| D | ieee80211.txt | 11 An example case for this can be tri-band wireless router with two
12 identical chipsets used for two different 5 GHz subbands. Using them
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| /Documentation/driver-api/iio/ |
| D | core.rst | 25 There are two ways for a user space application to interact with an IIO driver.
33 :doc:`SPI <../spi>` driver and will create two routines, probe and remove.
75 * a light sensor with two channels indicating the measurements in the visible
103 When there are multiple data channels per channel type we have two ways to
110 sensor can have two channels, one for infrared light and one for both
140 This channel's definition will generate two separate sysfs files for raw data
171 This will generate two separate attributes files for raw data retrieval:
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