Searched full:u32 (Results 1 – 25 of 199) sorted by relevance
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| /Documentation/virt/kvm/ |
| D | nested-vmx.txt | 82 u32 revision_id;
83 u32 abort;
85 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
86 u32 padding[7]; /* room for future expansion */
153 u32 pin_based_vm_exec_control;
154 u32 cpu_based_vm_exec_control;
155 u32 exception_bitmap;
156 u32 page_fault_error_code_mask;
157 u32 page_fault_error_code_match;
158 u32 cr3_target_count;
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| /Documentation/security/ |
| D | siphash.rst | 43 u64 siphash_1u32(u32, const siphash_key_t *key);
44 u64 siphash_2u32(u32, u32, const siphash_key_t *key);
45 u64 siphash_3u32(u32, u32, u32, const siphash_key_t *key);
46 u64 siphash_4u32(u32, u32, u32, u32, const siphash_key_t *key);
94 u32 counter;
148 u32 hsiphash(const void *data, size_t len, const hsiphash_key_t *key);
152 u32 hsiphash_1u32(u32, const hsiphash_key_t *key);
153 u32 hsiphash_2u32(u32, u32, const hsiphash_key_t *key);
154 u32 hsiphash_3u32(u32, u32, u32, const hsiphash_key_t *key);
155 u32 hsiphash_4u32(u32, u32, u32, u32, const hsiphash_key_t *key);
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,smsm.txt | 21 - u32 representing offset to the register within the syscon
22 - u32 representing the ipc bit within the register
26 Value type: <u32>
34 Value type: <u32>
39 Value type: <u32>
50 Value type: <u32>
56 Value type: <u32>
67 Value type: <u32>
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| D | qcom,smp2p.txt | 32 - u32 representing offset to the register within the syscon
33 - u32 representing the ipc bit within the register
37 Value type: <u32 array>
43 Value type: <u32>
48 Value type: <u32>
74 Value type: <u32>
79 Value type: <u32>
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| D | qcom,smd.txt | 37 - u32 representing offset to the register within the syscon
38 - u32 representing the ipc bit within the register
42 Value type: <u32>
48 Value type: <u32>
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-mtk-xsphy.txt | 21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
23 - mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on
46 - mediatek,eye-src : u32, the value of slew rate calibrate
47 - mediatek,eye-vrt : u32, the selection of VRT reference voltage
48 - mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage
49 - mediatek,efuse-intr : u32, the selection of Internal Resistor
52 - mediatek,efuse-intr : u32, the selection of Internal Resistor
53 - mediatek,efuse-tx-imp : u32, the selection of TX Impedance
54 - mediatek,efuse-rx-imp : u32, the selection of RX Impedance
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| /Documentation/devicetree/bindings/power/supply/ |
| D | qcom_smbb.txt | 45 Value type: <u32>; uA; range [100mA : 3A]
50 Value type: <u32>; uV; range [2.1V : 3.6V]
57 Value type: <u32>; uV; range [3.24V : 5V]
64 Value type: <u32>; uV; range [3.24V : 5V]
71 Value type: <u32>; uA; range [100mA : 3A]
78 Value type: <u32>; uV; range [3.24V : 5V]
85 Value type: <u32>; uV; range [4.2V : 9.6V]
90 Value type: <u32>; uA; range [100mA : 2.5A]
95 Value type: boolean: <u32> or <empty>
100 Value type: boolean: <u32> or <empty>
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| D | qcom,coincell-charger.txt | 14 Value type: <u32>
19 Value type: <u32>
25 Value type: <u32>
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| /Documentation/riscv/ |
| D | boot-image-header.rst | 15 u32 code0; /* Executable code */
16 u32 code1; /* Executable code */
20 u32 version; /* Version of this header */
21 u32 res1 = 0; /* Reserved */
24 u32 magic2 = 0x56534905; /* Magic number 2, little endian, "RSC\x05" */
25 u32 res4; /* Reserved for PE COFF offset */
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| /Documentation/devicetree/bindings/input/ |
| D | qcom,pm8xxx-keypad.txt | 44 Value type: <u32>
50 Value type: <u32>
56 Value type: <u32>
62 Value type: <u32>
68 Value type: <u32>
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| /Documentation/devicetree/bindings/misc/ |
| D | qcom,fastrpc.txt | 22 Value type: <u32>
27 Value type: <u32>
42 Value type: <u32>
47 Value type: <u32>
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| /Documentation/devicetree/bindings/ata/ |
| D | sata_highbank.txt | 21 - calxeda,led-order : a u32 array that map port numbers to offsets within the
23 - calxeda,tx-atten : a u32 array that contains TX attenuation override
26 - calxeda,pre-clocks : a u32 that indicates the number of additional clock
28 - calxeda,post-clocks: a u32 that indicates the number of additional clock
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| /Documentation/devicetree/bindings/power/ |
| D | domain-idle-state.txt | 16 Definition: u32 value representing worst case latency in
24 Definition: u32 value representing worst case latency
30 Definition: u32 value representing minimum residency duration
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| /Documentation/ |
| D | unaligned-memory-access.txt | 33 dealing with types such as u16, u32 and u64.
89 u32 field2;
121 u32 field2;
156 u32 fold = ((*(const u32 *)addr1) ^ (*(const u32 *)addr2)) |
185 void myfunc(u8 *data, u32 value)
188 *((u32 *) data) = cpu_to_le32(value);
211 void myfunc(u8 *data, u32 value)
214 *((u32 *) data) = cpu_to_le32(value);
220 void myfunc(u8 *data, u32 value)
224 put_unaligned(value, (u32 *) data);
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| /Documentation/devicetree/bindings/timer/ |
| D | csky,gx6605s-timer.txt | 22 Value type: <u32 u32>
30 Value type: <u32>
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| /Documentation/hid/ |
| D | hid-sensor.rst | 95 u32 usage_id,
103 u32 usage_id):
112 u32 usage_id, u32 attr_usage_id,
123 int sensor_hub_set_feature(struct hid_sensor_hub_device *hsdev, u32 report_id,
124 u32 field_index, s32 value);
132 int sensor_hub_get_feature(struct hid_sensor_hub_device *hsdev, u32 report_id,
133 u32 field_index, s32 *value);
142 u32 usage_id,
143 u32 attr_usage_id, u32 report_id);
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| /Documentation/devicetree/bindings/sound/ |
| D | rt5651.txt | 20 u32. Valid values:
31 u32, micbias over-current detection threshold in µA, valid values are
35 u32, micbias over-current detection scale-factor, valid values are:
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| D | qcom,q6asm.txt | 27 Value type: <u32>
35 Value type: <u32>
40 Value type: <u32>
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,versatile-fpga-irq.txt | 13 sources. The cell is a u32 and defines the interrupt number.
15 - clear-mask: a u32 number representing the mask written to clear all IRQs
17 - valid-mask: a u32 number representing a bit mask determining which of
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| /Documentation/devicetree/bindings/lpddr2/ |
| D | lpddr2-timings.txt | 5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
12 of type <u32> and the default unit is ps (pico seconds). Parameters with
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | qcom,spmi-vadc.txt | 25 Value type: <u32>
31 Value type: <u32>
36 Value type: <u32>
49 Value type: <u32>
63 Value type: <u32>
76 Value type: <u32 array>
101 Value type: <u32>
122 Value type: <u32>
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | qcom,pmic-mpp.txt | 43 Value type: <u32>
101 Value type: <u32>
133 Value type: <u32>
139 Value type: <u32>
146 Value type: <u32>
152 Value type: <u32>
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| /Documentation/filesystems/ |
| D | quota.txt | 42 QUOTA_NL_A_QTYPE (u32)
49 QUOTA_NL_A_WARNING (u32)
65 QUOTA_NL_A_DEV_MAJOR (u32)
67 QUOTA_NL_A_DEV_MINOR (u32)
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| /Documentation/devicetree/bindings/powerpc/ |
| D | ibm,powerpc-cpu-features.txt | 47 Value type: <u32>
85 Value type: <u32>
96 Value type: <u32> bit mask
112 Value type: <u32> bit mask
131 Value type: <u32> bit mask
150 Value type: <u32>
163 Value type: <u32>
176 Value type: <u32>
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| /Documentation/devicetree/bindings/csky/ |
| D | cpus.txt | 26 Value type: <u32>
30 Value type: <u32>
45 Value type: <u32>
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