| /Documentation/devicetree/bindings/serial/ |
| D | renesas,sci-serial.txt | 7 - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART.
8 - "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART.
9 - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART.
10 - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
11 - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
12 - "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART.
13 - "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART.
14 - "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART.
15 - "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART.
16 - "renesas,hscif-r8a7743" for R8A7743 (RZ/G1M) HSCIF compatible UART.
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| D | mvebu-uart.txt | 1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
6 - "marvell,armada-3700-uart" for the standard variant of the UART
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
20 (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx",
21 respectively the UART sum interrupt, the UART TX interrupt and
22 UART RX interrupt. A corresponding interrupt-names property must
25 (marvell,armada-3700-uart-ext): "uart-tx" and "uart-rx",
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| D | mtk-uart.txt | 1 * MediaTek Universal Asynchronous Receiver/Transmitter (UART)
5 * "mediatek,mt2701-uart" for MT2701 compatible UARTS
6 * "mediatek,mt2712-uart" for MT2712 compatible UARTS
7 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
8 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
9 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10 * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11 * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12 * "mediatek,mt6779-uart" for MT6779 compatible UARTS
13 * "mediatek,mt6795-uart" for MT6795 compatible UARTS
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| D | sirf-uart.txt | 4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
7 - interrupts : Should contain uart interrupt
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
18 uart0: uart@b0050000 {
20 compatible = "sirf,prima2-uart";
30 compatible = "sirf,prima2-usp-uart";
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| D | snps-dw-apb-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
7 title: Synopsys DesignWare ABP UART
20 - renesas,r9a06g032-uart
21 - renesas,r9a06g033-uart
22 - const: renesas,rzn1-uart
25 - rockchip,px30-uart
26 - rockchip,rk3036-uart
27 - rockchip,rk3066-uart
28 - rockchip,rk3188-uart
29 - rockchip,rk3288-uart
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| D | sprd-uart.txt | 1 * Spreadtrum serial UART
5 * "sprd,sc9836-uart"
6 * "sprd,sc9860-uart", "sprd,sc9836-uart"
11 "enable" for UART module enable clock,
12 "uart" for UART clock,
13 "source" for UART source (parent) clock.
15 UART clock and source clock are optional properties, but enable clock
24 compatible = "sprd,sc9860-uart",
25 "sprd,sc9836-uart";
30 clock-names = "enable", "uart", "source";
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| D | omap_serial.txt | 1 OMAP UART controller
4 - compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers
5 - compatible : should be "ti,am654-uart" for AM654 controllers
6 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
7 - compatible : should be "ti,omap3-uart" for OMAP3 controllers
8 - compatible : should be "ti,omap4-uart" for OMAP4 controllers
9 - compatible : should be "ti,am4372-uart" for AM437x controllers
10 - compatible : should be "ti,am3352-uart" for AM335x controllers
11 - compatible : should be "ti,dra742-uart" for DRA7x controllers
13 - interrupts or interrupts-extended : Should contain the uart interrupt
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| D | amlogic,meson-uart.yaml | 5 $id: "http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#"
8 title: Amlogic Meson SoC UART Serial Interface
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
25 - description: Always-on power domain UART controller
28 - amlogic,meson6-uart
29 - amlogic,meson8-uart
30 - amlogic,meson8b-uart
31 - amlogic,meson-gx-uart
32 - const: amlogic,meson-ao-uart
33 - description: Everything-Else power domain UART controller
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| D | samsung_uart.txt | 1 * Samsung's UART Controller
3 The Samsung's UART controller is used for interfacing SoC with serial
8 - "samsung,exynos4210-uart" - Exynos4210 SoC,
9 - "samsung,s3c2410-uart" - compatible with ports present on S3C2410 SoC,
10 - "samsung,s3c2412-uart" - compatible with ports present on S3C2412 SoC,
11 - "samsung,s3c2440-uart" - compatible with ports present on S3C2440 SoC,
12 - "samsung,s3c6400-uart" - compatible with ports present on S3C6400 SoC,
13 - "samsung,s5pv210-uart" - compatible with ports present on S5PV210 SoC.
22 - "uart" - controller bus clock,
33 - samsung,uart-fifosize: The fifo size supported by the UART channel
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| D | actions,owl-uart.txt | 1 Actions Semi Owl UART
4 - compatible : "actions,s500-uart", "actions,owl-uart" for S500
5 "actions,s900-uart", "actions,owl-uart" for S900
7 - interrupts : Should contain UART interrupt.
13 compatible = "actions,s500-uart", "actions,owl-uart";
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| D | fsl-imx-uart.txt | 1 * Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible : Should be "fsl,<soc>-uart"
6 - interrupts : Should contain uart interrupt
9 - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
13 you must enable either the "uart-has-rtscts" or the "rts-gpios"
14 properties. In case you use "uart-has-rtscts" the signal that controls
21 Note: Each uart controller should have an alias correctly numbered
31 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
34 uart-has-rtscts;
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| D | 8250.txt | 1 * UART (Universal Asynchronous Receiver/Transmitter)
11 - For Tegra20, must contain "nvidia,tegra20-uart"
12 - For other Tegra, must contain '"nvidia,<chip>-uart",
13 "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
15 - "nxp,lpc3220-uart"
16 - "ralink,rt2880-uart"
24 - "intel,xscale-uart"
25 - "ti,da830-uart"
28 - "nuvoton,npcm750-uart"
31 - interrupts : should contain uart interrupt.
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| D | ingenic,uart.txt | 1 * Ingenic SoC UART
5 - "ingenic,jz4740-uart",
6 - "ingenic,jz4760-uart",
7 - "ingenic,jz4770-uart",
8 - "ingenic,jz4775-uart",
9 - "ingenic,jz4780-uart",
10 - "ingenic,x1000-uart".
12 - interrupts : should contain uart interrupt.
20 compatible = "ingenic,jz4740-uart";
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| D | cirrus,clps711x-uart.txt | 1 * Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible: Should be "cirrus,ep7209-uart".
6 - interrupts: Should contain UART TX and RX interrupt.
7 - clocks: Should contain UART core clock number.
8 - syscon: Phandle to SYSCON node, which contain UART control bits.
14 Note: Each UART port should have an alias correctly numbered
22 uart1: uart@80000480 {
23 compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart";
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| D | cdns,uart.txt | 1 Binding for Cadence UART Controller
5 Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
6 Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
7 - reg: Should contain UART controller registers location and length.
8 - interrupts: Should contain UART controller interrupts.
9 - clocks: Must contain phandles to the UART clocks
21 uart@e0000000 {
22 compatible = "cdns,uart-r1p8";
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| D | serial.txt | 9 used as the UART's CTS line.
11 used as the UART's DCD line.
13 used as the UART's DSR line.
15 used as the UART's DTR line.
17 used as the UART's RNG line.
19 used as the UART's RTS line.
21 - uart-has-rtscts: The presence of this property indicates that the
22 UART has dedicated lines for RTS/CTS hardware flow control, and that
24 This depends on both the UART hardware and the board wiring.
33 compatible = "ti,am3352-uart", "ti,omap3-uart";
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| D | qcom,msm-uart.txt | 1 * MSM Serial UART
3 The MSM serial UART hardware is designed for low-speed use cases where a
9 - compatible: Should contain "qcom,msm-uart"
10 - reg: Should contain UART register location and length.
11 - interrupts: Should contain UART interrupt.
17 A uart device at 0xa9c00000 with interrupt 11.
20 compatible = "qcom,msm-uart";
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| D | sifive-serial.yaml | 7 title: SiFive asynchronous serial interface (UART)
20 - const: sifive,fu540-c000-uart
24 Should be something similar to "sifive,<chip>-uart"
25 for the UART as integrated on a particular chip,
26 and "sifive,uart<version>" for the general UART IP
29 UART HDL that corresponds to the IP block version
32 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
55 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
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| D | arc-uart.txt | 1 * Synopsys ARC UART : Non standard UART used in some of the ARC FPGA boards
4 - compatible : "snps,arc-uart"
7 - clock-frequency : the input clock frequency for the UART
8 - current-speed : baud rate for UART
13 compatible = "snps,arc-uart";
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| D | arm,mps2-uart.txt | 1 ARM MPS2 UART
4 - compatible : Should be "arm,mps2-uart"
6 - interrupts : Reference to the UART RX, TX and overrun interrupts
9 - clocks : The input clock of the UART
15 compatible = "arm,mps2-uart";
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| D | efm32-uart.txt | 1 * Energymicro efm32 UART
4 - compatible : Should be "energymicro,efm32-uart"
6 - interrupts : Should contain uart interrupt
15 uart@4000c400 {
16 compatible = "energymicro,efm32-uart";
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| D | qca,ar9330-uart.txt | 1 * Qualcomm Atheros AR9330 High-Speed UART
5 - compatible: Must be "qca,ar9330-uart"
16 Each UART port must have an alias correctly numbered in "aliases"
25 uart0: uart@18020000 {
26 compatible = "qca,ar9330-uart";
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| D | altera_uart.txt | 1 Altera UART
4 - compatible : should be "ALTR,uart-1.0" <DEPRECATED>
5 - compatible : should be "altr,uart-1.0"
8 - clock-frequency : frequency of the clock input to the UART
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | serial.txt | 4 - fsl,cpm1-smc-uart
5 - fsl,cpm2-smc-uart
6 - fsl,cpm1-scc-uart
7 - fsl,cpm2-scc-uart
8 - fsl,qe-uart
23 compatible = "fsl,mpc8272-scc-uart",
24 "fsl,cpm2-scc-uart";
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-mt7622.txt | 196 "pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog"
306 "uart0_0_tx_rx" "uart" 6, 7
307 "uart1_0_tx_rx" "uart" 55, 56
308 "uart1_0_rts_cts" "uart" 57, 58
309 "uart1_1_tx_rx" "uart" 73, 74
310 "uart1_1_rts_cts" "uart" 75, 76
311 "uart2_0_tx_rx" "uart" 3, 4
312 "uart2_0_rts_cts" "uart" 1, 2
313 "uart2_1_tx_rx" "uart" 51, 52
314 "uart2_1_rts_cts" "uart" 53, 54
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