Searched full:wired (Results 1 – 25 of 100) sorted by relevance
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | img,pdc-intc.txt | 82 * An SoC peripheral that is wired through the PDC.
85 // The interrupt controller that this device is wired to.
96 * An interrupt generating device that is wired to a SysWake pin.
99 // The interrupt controller that this device is wired to.
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| D | marvell,sei.txt | 10 AP and is wired while a second set comes from the CPs by the mean of
19 - #interrupt-cells: number of cells to define an SEI wired interrupt
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| D | img,meta-intc.txt | 71 * An interrupt generating device that is wired to a Meta external
80 // The interrupt controller that this device is wired to.
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| D | open-pic.txt | 81 * An interrupt generating device that is wired to an Open PIC.
89 // The interrupt controller that this device is wired to.
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| D | intel,ce4100-ioapic.txt | 15 The first number (P) represents the interrupt pin which is wired to the
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| D | openrisc,ompic.txt | 12 - interrupts : Specifies the interrupt line to which the ompic is wired.
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| D | marvell,gicp.txt | 6 located in the Marvell CP110 to turn wired interrupts inside the CP
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| D | atmel,aic.txt | 37 * An interrupt generating device that is wired to an AIC.
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| D | arm,vic.txt | 23 at source 31 at MSb. A bit that is set means that the source is wired and
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| /Documentation/devicetree/bindings/media/ |
| D | st-rc.txt | 12 be present iff the rx pins are wired up.
15 be present iff the tx pins are wired up.
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| /Documentation/devicetree/bindings/iommu/ |
| D | arm,smmu-v3.txt | 18 - interrupts : Non-secure interrupt list describing the wired
20 interrupt-names. If no wired interrupts are
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | sii902x.txt | 14 is wired, <1> if the both are wired. HDMI audio is
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| /Documentation/devicetree/bindings/sound/ |
| D | adi,adau17x1.txt | 14 and ADDR1, as wired in hardware.
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| D | fsl,ssi.txt | 74 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
78 DMA controller to use, but the channels themselves are hard-wired. The
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| D | adi,adau1701.txt | 7 and ADDR1, as wired in hardware.
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| /Documentation/devicetree/bindings/mips/ |
| D | cpu_irq.txt | 6 With the irq_domain in place we can describe how the 8 IRQs are wired to the
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| /Documentation/hwmon/ |
| D | w83773g.rst | 27 The chip is wired over I2C/SMBus and specified over a temperature
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| D | via686a.rst | 80 in which case the sensor inputs will not be wired. This is the case of
84 not wired for hardware monitoring.
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| D | smsc47m192.rst | 57 the motherboard has this input wired to VID4.
87 would typically be wired to the diode inside the CPU)
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-iio-adc-envelope-detector | 8 of a comparator wired to an interrupt pin. Like so:
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| /Documentation/devicetree/bindings/soc/fsl/ |
| D | guts.txt | 23 is wired to reset upon setting the HRESET_REQ bit in this register).
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| /Documentation/devicetree/bindings/clock/ |
| D | qcom,spmi-clkdiv.txt | 4 These clocks are typically wired through alternate functions on
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| /Documentation/devicetree/bindings/mfd/ |
| D | twl4030-power.txt | 23 depending on how the external oscillator is wired.
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| /Documentation/networking/ |
| D | ipsec.txt | 33 The result is much more wired to the user when ping peer with different
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| /Documentation/scsi/ |
| D | 53c700.txt | 31 driver, you need to know three things about the way the chip is wired
39 the SCSI Id from the card bios or whether the chip is wired for
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