1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
23 Copyright (C) 2013-2018 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
27 Permission is hereby granted, free of charge, to any person obtaining
28 a copy of this software and associated documentation files (the
29 "Software"), to deal in the Software without restriction, including
30 without limitation the rights to use, copy, modify, merge, publish,
31 distribute, sublicense, and/or sell copies of the Software, and to
32 permit persons to whom the Software is furnished to do so, subject to
33 the following conditions:
34
35 The above copyright notice and this permission notice (including the
36 next paragraph) shall be included in all copies or substantial
37 portions of the Software.
38
39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48
49 enum vgt_event_type {
50 VS_DEALLOC = 0,
51 PS_DEALLOC = 1,
52 VS_DONE_TS = 2,
53 PS_DONE_TS = 3,
54 CACHE_FLUSH_TS = 4,
55 CONTEXT_DONE = 5,
56 CACHE_FLUSH = 6,
57 HLSQ_FLUSH = 7,
58 VIZQUERY_START = 7,
59 VIZQUERY_END = 8,
60 SC_WAIT_WC = 9,
61 RST_PIX_CNT = 13,
62 RST_VTX_CNT = 14,
63 TILE_FLUSH = 15,
64 STAT_EVENT = 16,
65 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
66 ZPASS_DONE = 21,
67 CACHE_FLUSH_AND_INV_EVENT = 22,
68 PERFCOUNTER_START = 23,
69 PERFCOUNTER_STOP = 24,
70 VS_FETCH_DONE = 27,
71 FACENESS_FLUSH = 28,
72 FLUSH_SO_0 = 17,
73 FLUSH_SO_1 = 18,
74 FLUSH_SO_2 = 19,
75 FLUSH_SO_3 = 20,
76 PC_CCU_INVALIDATE_DEPTH = 24,
77 PC_CCU_INVALIDATE_COLOR = 25,
78 UNK_1C = 28,
79 UNK_1D = 29,
80 BLIT = 30,
81 UNK_25 = 37,
82 LRZ_FLUSH = 38,
83 UNK_2C = 44,
84 UNK_2D = 45,
85 };
86
87 enum pc_di_primtype {
88 DI_PT_NONE = 0,
89 DI_PT_POINTLIST_PSIZE = 1,
90 DI_PT_LINELIST = 2,
91 DI_PT_LINESTRIP = 3,
92 DI_PT_TRILIST = 4,
93 DI_PT_TRIFAN = 5,
94 DI_PT_TRISTRIP = 6,
95 DI_PT_LINELOOP = 7,
96 DI_PT_RECTLIST = 8,
97 DI_PT_POINTLIST = 9,
98 DI_PT_LINE_ADJ = 10,
99 DI_PT_LINESTRIP_ADJ = 11,
100 DI_PT_TRI_ADJ = 12,
101 DI_PT_TRISTRIP_ADJ = 13,
102 };
103
104 enum pc_di_src_sel {
105 DI_SRC_SEL_DMA = 0,
106 DI_SRC_SEL_IMMEDIATE = 1,
107 DI_SRC_SEL_AUTO_INDEX = 2,
108 DI_SRC_SEL_RESERVED = 3,
109 };
110
111 enum pc_di_face_cull_sel {
112 DI_FACE_CULL_NONE = 0,
113 DI_FACE_CULL_FETCH = 1,
114 DI_FACE_BACKFACE_CULL = 2,
115 DI_FACE_FRONTFACE_CULL = 3,
116 };
117
118 enum pc_di_index_size {
119 INDEX_SIZE_IGN = 0,
120 INDEX_SIZE_16_BIT = 0,
121 INDEX_SIZE_32_BIT = 1,
122 INDEX_SIZE_8_BIT = 2,
123 INDEX_SIZE_INVALID = 0,
124 };
125
126 enum pc_di_vis_cull_mode {
127 IGNORE_VISIBILITY = 0,
128 USE_VISIBILITY = 1,
129 };
130
131 enum adreno_pm4_packet_type {
132 CP_TYPE0_PKT = 0,
133 CP_TYPE1_PKT = 0x40000000,
134 CP_TYPE2_PKT = 0x80000000,
135 CP_TYPE3_PKT = 0xc0000000,
136 CP_TYPE4_PKT = 0x40000000,
137 CP_TYPE7_PKT = 0x70000000,
138 };
139
140 enum adreno_pm4_type3_packets {
141 CP_ME_INIT = 72,
142 CP_NOP = 16,
143 CP_PREEMPT_ENABLE = 28,
144 CP_PREEMPT_TOKEN = 30,
145 CP_INDIRECT_BUFFER = 63,
146 CP_INDIRECT_BUFFER_PFD = 55,
147 CP_WAIT_FOR_IDLE = 38,
148 CP_WAIT_REG_MEM = 60,
149 CP_WAIT_REG_EQ = 82,
150 CP_WAIT_REG_GTE = 83,
151 CP_WAIT_UNTIL_READ = 92,
152 CP_WAIT_IB_PFD_COMPLETE = 93,
153 CP_REG_RMW = 33,
154 CP_SET_BIN_DATA = 47,
155 CP_SET_BIN_DATA5 = 47,
156 CP_REG_TO_MEM = 62,
157 CP_MEM_WRITE = 61,
158 CP_MEM_WRITE_CNTR = 79,
159 CP_COND_EXEC = 68,
160 CP_COND_WRITE = 69,
161 CP_COND_WRITE5 = 69,
162 CP_EVENT_WRITE = 70,
163 CP_EVENT_WRITE_SHD = 88,
164 CP_EVENT_WRITE_CFL = 89,
165 CP_EVENT_WRITE_ZPD = 91,
166 CP_RUN_OPENCL = 49,
167 CP_DRAW_INDX = 34,
168 CP_DRAW_INDX_2 = 54,
169 CP_DRAW_INDX_BIN = 52,
170 CP_DRAW_INDX_2_BIN = 53,
171 CP_VIZ_QUERY = 35,
172 CP_SET_STATE = 37,
173 CP_SET_CONSTANT = 45,
174 CP_IM_LOAD = 39,
175 CP_IM_LOAD_IMMEDIATE = 43,
176 CP_LOAD_CONSTANT_CONTEXT = 46,
177 CP_INVALIDATE_STATE = 59,
178 CP_SET_SHADER_BASES = 74,
179 CP_SET_BIN_MASK = 80,
180 CP_SET_BIN_SELECT = 81,
181 CP_CONTEXT_UPDATE = 94,
182 CP_INTERRUPT = 64,
183 CP_IM_STORE = 44,
184 CP_SET_DRAW_INIT_FLAGS = 75,
185 CP_SET_PROTECTED_MODE = 95,
186 CP_BOOTSTRAP_UCODE = 111,
187 CP_LOAD_STATE = 48,
188 CP_LOAD_STATE4 = 48,
189 CP_COND_INDIRECT_BUFFER_PFE = 58,
190 CP_COND_INDIRECT_BUFFER_PFD = 50,
191 CP_INDIRECT_BUFFER_PFE = 63,
192 CP_SET_BIN = 76,
193 CP_TEST_TWO_MEMS = 113,
194 CP_REG_WR_NO_CTXT = 120,
195 CP_RECORD_PFP_TIMESTAMP = 17,
196 CP_SET_SECURE_MODE = 102,
197 CP_WAIT_FOR_ME = 19,
198 CP_SET_DRAW_STATE = 67,
199 CP_DRAW_INDX_OFFSET = 56,
200 CP_DRAW_INDIRECT = 40,
201 CP_DRAW_INDX_INDIRECT = 41,
202 CP_DRAW_AUTO = 36,
203 CP_UNKNOWN_19 = 25,
204 CP_UNKNOWN_1A = 26,
205 CP_UNKNOWN_4E = 78,
206 CP_WIDE_REG_WRITE = 116,
207 CP_SCRATCH_TO_REG = 77,
208 CP_REG_TO_SCRATCH = 74,
209 CP_WAIT_MEM_WRITES = 18,
210 CP_COND_REG_EXEC = 71,
211 CP_MEM_TO_REG = 66,
212 CP_EXEC_CS_INDIRECT = 65,
213 CP_EXEC_CS = 51,
214 CP_PERFCOUNTER_ACTION = 80,
215 CP_SMMU_TABLE_UPDATE = 83,
216 CP_SET_MARKER = 101,
217 CP_SET_PSEUDO_REG = 86,
218 CP_CONTEXT_REG_BUNCH = 92,
219 CP_YIELD_ENABLE = 28,
220 CP_SKIP_IB2_ENABLE_GLOBAL = 29,
221 CP_SKIP_IB2_ENABLE_LOCAL = 35,
222 CP_SET_SUBDRAW_SIZE = 53,
223 CP_SET_VISIBILITY_OVERRIDE = 100,
224 CP_PREEMPT_ENABLE_GLOBAL = 105,
225 CP_PREEMPT_ENABLE_LOCAL = 106,
226 CP_CONTEXT_SWITCH_YIELD = 107,
227 CP_SET_RENDER_MODE = 108,
228 CP_COMPUTE_CHECKPOINT = 110,
229 CP_MEM_TO_MEM = 115,
230 CP_BLIT = 44,
231 CP_REG_TEST = 57,
232 CP_SET_MODE = 99,
233 CP_LOAD_STATE6_GEOM = 50,
234 CP_LOAD_STATE6_FRAG = 52,
235 IN_IB_PREFETCH_END = 23,
236 IN_SUBBLK_PREFETCH = 31,
237 IN_INSTR_PREFETCH = 32,
238 IN_INSTR_MATCH = 71,
239 IN_CONST_PREFETCH = 73,
240 IN_INCR_UPDT_STATE = 85,
241 IN_INCR_UPDT_CONST = 86,
242 IN_INCR_UPDT_INSTR = 87,
243 PKT4 = 4,
244 CP_UNK_A6XX_14 = 20,
245 CP_UNK_A6XX_36 = 54,
246 CP_UNK_A6XX_55 = 85,
247 CP_REG_WRITE = 109,
248 };
249
250 enum adreno_state_block {
251 SB_VERT_TEX = 0,
252 SB_VERT_MIPADDR = 1,
253 SB_FRAG_TEX = 2,
254 SB_FRAG_MIPADDR = 3,
255 SB_VERT_SHADER = 4,
256 SB_GEOM_SHADER = 5,
257 SB_FRAG_SHADER = 6,
258 SB_COMPUTE_SHADER = 7,
259 };
260
261 enum adreno_state_type {
262 ST_SHADER = 0,
263 ST_CONSTANTS = 1,
264 };
265
266 enum adreno_state_src {
267 SS_DIRECT = 0,
268 SS_INVALID_ALL_IC = 2,
269 SS_INVALID_PART_IC = 3,
270 SS_INDIRECT = 4,
271 SS_INDIRECT_TCM = 5,
272 SS_INDIRECT_STM = 6,
273 };
274
275 enum a4xx_state_block {
276 SB4_VS_TEX = 0,
277 SB4_HS_TEX = 1,
278 SB4_DS_TEX = 2,
279 SB4_GS_TEX = 3,
280 SB4_FS_TEX = 4,
281 SB4_CS_TEX = 5,
282 SB4_VS_SHADER = 8,
283 SB4_HS_SHADER = 9,
284 SB4_DS_SHADER = 10,
285 SB4_GS_SHADER = 11,
286 SB4_FS_SHADER = 12,
287 SB4_CS_SHADER = 13,
288 SB4_SSBO = 14,
289 SB4_CS_SSBO = 15,
290 };
291
292 enum a4xx_state_type {
293 ST4_SHADER = 0,
294 ST4_CONSTANTS = 1,
295 };
296
297 enum a4xx_state_src {
298 SS4_DIRECT = 0,
299 SS4_INDIRECT = 2,
300 };
301
302 enum a6xx_state_block {
303 SB6_VS_TEX = 0,
304 SB6_HS_TEX = 1,
305 SB6_DS_TEX = 2,
306 SB6_GS_TEX = 3,
307 SB6_FS_TEX = 4,
308 SB6_CS_TEX = 5,
309 SB6_VS_SHADER = 8,
310 SB6_HS_SHADER = 9,
311 SB6_DS_SHADER = 10,
312 SB6_GS_SHADER = 11,
313 SB6_FS_SHADER = 12,
314 SB6_CS_SHADER = 13,
315 SB6_SSBO = 14,
316 SB6_CS_SSBO = 15,
317 };
318
319 enum a6xx_state_type {
320 ST6_SHADER = 0,
321 ST6_CONSTANTS = 1,
322 };
323
324 enum a6xx_state_src {
325 SS6_DIRECT = 0,
326 SS6_INDIRECT = 2,
327 };
328
329 enum a4xx_index_size {
330 INDEX4_SIZE_8_BIT = 0,
331 INDEX4_SIZE_16_BIT = 1,
332 INDEX4_SIZE_32_BIT = 2,
333 };
334
335 enum cp_cond_function {
336 WRITE_ALWAYS = 0,
337 WRITE_LT = 1,
338 WRITE_LE = 2,
339 WRITE_EQ = 3,
340 WRITE_NE = 4,
341 WRITE_GE = 5,
342 WRITE_GT = 6,
343 };
344
345 enum render_mode_cmd {
346 BYPASS = 1,
347 BINNING = 2,
348 GMEM = 3,
349 BLIT2D = 5,
350 BLIT2DSCALE = 7,
351 END2D = 8,
352 };
353
354 enum cp_blit_cmd {
355 BLIT_OP_FILL = 0,
356 BLIT_OP_COPY = 1,
357 BLIT_OP_SCALE = 3,
358 };
359
360 enum a6xx_render_mode {
361 RM6_BYPASS = 1,
362 RM6_BINNING = 2,
363 RM6_GMEM = 4,
364 RM6_BLIT2D = 5,
365 RM6_RESOLVE = 6,
366 RM6_BLIT2DSCALE = 12,
367 };
368
369 enum pseudo_reg {
370 SMMU_INFO = 0,
371 NON_SECURE_SAVE_ADDR = 1,
372 SECURE_SAVE_ADDR = 2,
373 NON_PRIV_SAVE_ADDR = 3,
374 COUNTER = 4,
375 };
376
377 #define REG_CP_LOAD_STATE_0 0x00000000
378 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
379 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
CP_LOAD_STATE_0_DST_OFF(uint32_t val)380 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
381 {
382 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
383 }
384 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
385 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)386 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
387 {
388 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
389 }
390 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
391 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)392 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
393 {
394 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
395 }
396 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
397 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)398 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
399 {
400 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
401 }
402
403 #define REG_CP_LOAD_STATE_1 0x00000001
404 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
405 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)406 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
407 {
408 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
409 }
410 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
411 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)412 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
413 {
414 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
415 }
416
417 #define REG_CP_LOAD_STATE4_0 0x00000000
418 #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff
419 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
CP_LOAD_STATE4_0_DST_OFF(uint32_t val)420 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
421 {
422 return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
423 }
424 #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
425 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16
CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)426 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
427 {
428 return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
429 }
430 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
431 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18
CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)432 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
433 {
434 return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
435 }
436 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
437 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22
CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)438 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
439 {
440 return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
441 }
442
443 #define REG_CP_LOAD_STATE4_1 0x00000001
444 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
445 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)446 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
447 {
448 return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
449 }
450 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
451 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)452 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
453 {
454 return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
455 }
456
457 #define REG_CP_LOAD_STATE4_2 0x00000002
458 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
459 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)460 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
461 {
462 return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
463 }
464
465 #define REG_CP_LOAD_STATE6_0 0x00000000
466 #define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff
467 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0
CP_LOAD_STATE6_0_DST_OFF(uint32_t val)468 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
469 {
470 return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
471 }
472 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x00004000
473 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14
CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)474 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
475 {
476 return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;
477 }
478 #define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000
479 #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16
CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)480 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)
481 {
482 return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;
483 }
484 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000
485 #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18
CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)486 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)
487 {
488 return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;
489 }
490 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000
491 #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22
CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)492 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)
493 {
494 return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;
495 }
496
497 #define REG_CP_LOAD_STATE6_1 0x00000001
498 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc
499 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2
CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)500 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)
501 {
502 return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;
503 }
504
505 #define REG_CP_LOAD_STATE6_2 0x00000002
506 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
507 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0
CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)508 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)
509 {
510 return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;
511 }
512
513 #define REG_CP_DRAW_INDX_0 0x00000000
514 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
515 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)516 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
517 {
518 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
519 }
520
521 #define REG_CP_DRAW_INDX_1 0x00000001
522 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
523 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)524 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
525 {
526 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
527 }
528 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
529 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)530 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
531 {
532 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
533 }
534 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
535 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)536 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
537 {
538 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
539 }
540 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
541 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)542 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
543 {
544 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
545 }
546 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
547 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
548 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
549 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
550 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)551 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
552 {
553 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
554 }
555
556 #define REG_CP_DRAW_INDX_2 0x00000002
557 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
558 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)559 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
560 {
561 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
562 }
563
564 #define REG_CP_DRAW_INDX_3 0x00000003
565 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
566 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
CP_DRAW_INDX_3_INDX_BASE(uint32_t val)567 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
568 {
569 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
570 }
571
572 #define REG_CP_DRAW_INDX_4 0x00000004
573 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
574 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)575 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
576 {
577 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
578 }
579
580 #define REG_CP_DRAW_INDX_2_0 0x00000000
581 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
582 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)583 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
584 {
585 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
586 }
587
588 #define REG_CP_DRAW_INDX_2_1 0x00000001
589 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
590 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)591 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
592 {
593 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
594 }
595 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
596 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)597 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
598 {
599 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
600 }
601 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
602 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)603 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
604 {
605 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
606 }
607 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
608 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)609 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
610 {
611 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
612 }
613 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
614 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
615 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
616 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
617 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)618 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
619 {
620 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
621 }
622
623 #define REG_CP_DRAW_INDX_2_2 0x00000002
624 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
625 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)626 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
627 {
628 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
629 }
630
631 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
632 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
633 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)634 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
635 {
636 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
637 }
638 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
639 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)640 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
641 {
642 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
643 }
644 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
645 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)646 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
647 {
648 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
649 }
650 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
651 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)652 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
653 {
654 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
655 }
656 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
657 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)658 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
659 {
660 return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
661 }
662
663 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
664 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
665 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)666 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
667 {
668 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
669 }
670
671 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
672 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
673 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)674 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
675 {
676 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
677 }
678
679 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
680
681 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
682 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
683 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)684 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
685 {
686 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
687 }
688
689 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
690 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
691 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)692 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
693 {
694 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
695 }
696
697 #define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000
698 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
699 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0
A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)700 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
701 {
702 return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
703 }
704 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
705 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6
A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)706 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
707 {
708 return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
709 }
710 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300
711 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8
A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)712 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
713 {
714 return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
715 }
716 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
717 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10
A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)718 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
719 {
720 return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
721 }
722 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK 0x01f00000
723 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT 20
A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)724 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)
725 {
726 return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK;
727 }
728
729 #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
730 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
731 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0
A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)732 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
733 {
734 return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
735 }
736
737
738 #define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002
739 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
740 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)741 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
742 {
743 return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
744 }
745
746 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000
747 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
748 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)749 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
750 {
751 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
752 }
753 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
754 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6
A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)755 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
756 {
757 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
758 }
759 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300
760 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8
A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)761 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
762 {
763 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
764 }
765 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
766 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10
A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)767 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
768 {
769 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
770 }
771 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK 0x01f00000
772 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT 20
A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)773 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)
774 {
775 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK;
776 }
777
778
779 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
780 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff
781 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0
A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)782 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
783 {
784 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
785 }
786
787 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
788 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff
789 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0
A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)790 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
791 {
792 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
793 }
794
795 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
796 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff
797 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0
A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)798 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
799 {
800 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
801 }
802
803
804 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
805 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
806 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)807 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
808 {
809 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
810 }
811
812 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
813 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff
814 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0
A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)815 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
816 {
817 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
818 }
819
820 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
821 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
822 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)823 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
824 {
825 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
826 }
827
828 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004
829 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff
830 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0
A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)831 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
832 {
833 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
834 }
835
836 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005
837 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff
838 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0
A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)839 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
840 {
841 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
842 }
843
REG_CP_SET_DRAW_STATE_(uint32_t i0)844 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
845
REG_CP_SET_DRAW_STATE__0(uint32_t i0)846 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
847 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
848 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
CP_SET_DRAW_STATE__0_COUNT(uint32_t val)849 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
850 {
851 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
852 }
853 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
854 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
855 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
856 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
857 #define CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK 0x00f00000
858 #define CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT 20
CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val)859 static inline uint32_t CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val)
860 {
861 return ((val) << CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT) & CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK;
862 }
863 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
864 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)865 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
866 {
867 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
868 }
869
REG_CP_SET_DRAW_STATE__1(uint32_t i0)870 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
871 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
872 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)873 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
874 {
875 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
876 }
877
REG_CP_SET_DRAW_STATE__2(uint32_t i0)878 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
879 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
880 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)881 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
882 {
883 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
884 }
885
886 #define REG_CP_SET_BIN_0 0x00000000
887
888 #define REG_CP_SET_BIN_1 0x00000001
889 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
890 #define CP_SET_BIN_1_X1__SHIFT 0
CP_SET_BIN_1_X1(uint32_t val)891 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
892 {
893 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
894 }
895 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
896 #define CP_SET_BIN_1_Y1__SHIFT 16
CP_SET_BIN_1_Y1(uint32_t val)897 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
898 {
899 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
900 }
901
902 #define REG_CP_SET_BIN_2 0x00000002
903 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
904 #define CP_SET_BIN_2_X2__SHIFT 0
CP_SET_BIN_2_X2(uint32_t val)905 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
906 {
907 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
908 }
909 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
910 #define CP_SET_BIN_2_Y2__SHIFT 16
CP_SET_BIN_2_Y2(uint32_t val)911 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
912 {
913 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
914 }
915
916 #define REG_CP_SET_BIN_DATA_0 0x00000000
917 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
918 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)919 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
920 {
921 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
922 }
923
924 #define REG_CP_SET_BIN_DATA_1 0x00000001
925 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
926 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)927 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
928 {
929 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
930 }
931
932 #define REG_CP_SET_BIN_DATA5_0 0x00000000
933 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
934 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)935 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
936 {
937 return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
938 }
939 #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
940 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)941 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
942 {
943 return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
944 }
945
946 #define REG_CP_SET_BIN_DATA5_1 0x00000001
947 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
948 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)949 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
950 {
951 return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
952 }
953
954 #define REG_CP_SET_BIN_DATA5_2 0x00000002
955 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
956 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)957 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
958 {
959 return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
960 }
961
962 #define REG_CP_SET_BIN_DATA5_3 0x00000003
963 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
964 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)965 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
966 {
967 return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
968 }
969
970 #define REG_CP_SET_BIN_DATA5_4 0x00000004
971 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
972 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)973 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
974 {
975 return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
976 }
977
978 #define REG_CP_SET_BIN_DATA5_5 0x00000005
979 #define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK 0xffffffff
980 #define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT 0
CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO(uint32_t val)981 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO(uint32_t val)
982 {
983 return ((val) << CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK;
984 }
985
986 #define REG_CP_SET_BIN_DATA5_6 0x00000006
987 #define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK 0xffffffff
988 #define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT 0
CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO(uint32_t val)989 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO(uint32_t val)
990 {
991 return ((val) << CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK;
992 }
993
994 #define REG_CP_REG_TO_MEM_0 0x00000000
995 #define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
996 #define CP_REG_TO_MEM_0_REG__SHIFT 0
CP_REG_TO_MEM_0_REG(uint32_t val)997 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
998 {
999 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
1000 }
1001 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
1002 #define CP_REG_TO_MEM_0_CNT__SHIFT 19
CP_REG_TO_MEM_0_CNT(uint32_t val)1003 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
1004 {
1005 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
1006 }
1007 #define CP_REG_TO_MEM_0_64B 0x40000000
1008 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
1009
1010 #define REG_CP_REG_TO_MEM_1 0x00000001
1011 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
1012 #define CP_REG_TO_MEM_1_DEST__SHIFT 0
CP_REG_TO_MEM_1_DEST(uint32_t val)1013 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
1014 {
1015 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
1016 }
1017
1018 #define REG_CP_REG_TO_MEM_2 0x00000002
1019 #define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff
1020 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0
CP_REG_TO_MEM_2_DEST_HI(uint32_t val)1021 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)
1022 {
1023 return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;
1024 }
1025
1026 #define REG_CP_MEM_TO_REG_0 0x00000000
1027 #define CP_MEM_TO_REG_0_REG__MASK 0x0000ffff
1028 #define CP_MEM_TO_REG_0_REG__SHIFT 0
CP_MEM_TO_REG_0_REG(uint32_t val)1029 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
1030 {
1031 return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;
1032 }
1033 #define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000
1034 #define CP_MEM_TO_REG_0_CNT__SHIFT 19
CP_MEM_TO_REG_0_CNT(uint32_t val)1035 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)
1036 {
1037 return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;
1038 }
1039 #define CP_MEM_TO_REG_0_64B 0x40000000
1040 #define CP_MEM_TO_REG_0_ACCUMULATE 0x80000000
1041
1042 #define REG_CP_MEM_TO_REG_1 0x00000001
1043 #define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff
1044 #define CP_MEM_TO_REG_1_SRC__SHIFT 0
CP_MEM_TO_REG_1_SRC(uint32_t val)1045 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)
1046 {
1047 return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;
1048 }
1049
1050 #define REG_CP_MEM_TO_REG_2 0x00000002
1051 #define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff
1052 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0
CP_MEM_TO_REG_2_SRC_HI(uint32_t val)1053 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)
1054 {
1055 return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;
1056 }
1057
1058 #define REG_CP_MEM_TO_MEM_0 0x00000000
1059 #define CP_MEM_TO_MEM_0_NEG_A 0x00000001
1060 #define CP_MEM_TO_MEM_0_NEG_B 0x00000002
1061 #define CP_MEM_TO_MEM_0_NEG_C 0x00000004
1062 #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
1063
1064 #define REG_CP_COND_WRITE_0 0x00000000
1065 #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
1066 #define CP_COND_WRITE_0_FUNCTION__SHIFT 0
CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)1067 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
1068 {
1069 return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
1070 }
1071 #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
1072 #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
1073
1074 #define REG_CP_COND_WRITE_1 0x00000001
1075 #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
1076 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
CP_COND_WRITE_1_POLL_ADDR(uint32_t val)1077 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
1078 {
1079 return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
1080 }
1081
1082 #define REG_CP_COND_WRITE_2 0x00000002
1083 #define CP_COND_WRITE_2_REF__MASK 0xffffffff
1084 #define CP_COND_WRITE_2_REF__SHIFT 0
CP_COND_WRITE_2_REF(uint32_t val)1085 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
1086 {
1087 return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
1088 }
1089
1090 #define REG_CP_COND_WRITE_3 0x00000003
1091 #define CP_COND_WRITE_3_MASK__MASK 0xffffffff
1092 #define CP_COND_WRITE_3_MASK__SHIFT 0
CP_COND_WRITE_3_MASK(uint32_t val)1093 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
1094 {
1095 return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
1096 }
1097
1098 #define REG_CP_COND_WRITE_4 0x00000004
1099 #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
1100 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)1101 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
1102 {
1103 return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
1104 }
1105
1106 #define REG_CP_COND_WRITE_5 0x00000005
1107 #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
1108 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
CP_COND_WRITE_5_WRITE_DATA(uint32_t val)1109 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
1110 {
1111 return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
1112 }
1113
1114 #define REG_CP_COND_WRITE5_0 0x00000000
1115 #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
1116 #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)1117 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
1118 {
1119 return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
1120 }
1121 #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
1122 #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
1123
1124 #define REG_CP_COND_WRITE5_1 0x00000001
1125 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
1126 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)1127 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
1128 {
1129 return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
1130 }
1131
1132 #define REG_CP_COND_WRITE5_2 0x00000002
1133 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
1134 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)1135 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
1136 {
1137 return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
1138 }
1139
1140 #define REG_CP_COND_WRITE5_3 0x00000003
1141 #define CP_COND_WRITE5_3_REF__MASK 0xffffffff
1142 #define CP_COND_WRITE5_3_REF__SHIFT 0
CP_COND_WRITE5_3_REF(uint32_t val)1143 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
1144 {
1145 return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
1146 }
1147
1148 #define REG_CP_COND_WRITE5_4 0x00000004
1149 #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
1150 #define CP_COND_WRITE5_4_MASK__SHIFT 0
CP_COND_WRITE5_4_MASK(uint32_t val)1151 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
1152 {
1153 return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
1154 }
1155
1156 #define REG_CP_COND_WRITE5_5 0x00000005
1157 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
1158 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)1159 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
1160 {
1161 return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
1162 }
1163
1164 #define REG_CP_COND_WRITE5_6 0x00000006
1165 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
1166 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)1167 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
1168 {
1169 return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
1170 }
1171
1172 #define REG_CP_COND_WRITE5_7 0x00000007
1173 #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
1174 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)1175 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
1176 {
1177 return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
1178 }
1179
1180 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000
1181
1182 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001
1183 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
1184 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
CP_DISPATCH_COMPUTE_1_X(uint32_t val)1185 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
1186 {
1187 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
1188 }
1189
1190 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002
1191 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
1192 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
CP_DISPATCH_COMPUTE_2_Y(uint32_t val)1193 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
1194 {
1195 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
1196 }
1197
1198 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003
1199 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
1200 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
CP_DISPATCH_COMPUTE_3_Z(uint32_t val)1201 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
1202 {
1203 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
1204 }
1205
1206 #define REG_CP_SET_RENDER_MODE_0 0x00000000
1207 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
1208 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)1209 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
1210 {
1211 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
1212 }
1213
1214 #define REG_CP_SET_RENDER_MODE_1 0x00000001
1215 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
1216 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)1217 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
1218 {
1219 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
1220 }
1221
1222 #define REG_CP_SET_RENDER_MODE_2 0x00000002
1223 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
1224 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)1225 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
1226 {
1227 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
1228 }
1229
1230 #define REG_CP_SET_RENDER_MODE_3 0x00000003
1231 #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
1232 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
1233
1234 #define REG_CP_SET_RENDER_MODE_4 0x00000004
1235
1236 #define REG_CP_SET_RENDER_MODE_5 0x00000005
1237 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
1238 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)1239 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
1240 {
1241 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
1242 }
1243
1244 #define REG_CP_SET_RENDER_MODE_6 0x00000006
1245 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
1246 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)1247 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
1248 {
1249 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
1250 }
1251
1252 #define REG_CP_SET_RENDER_MODE_7 0x00000007
1253 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
1254 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)1255 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
1256 {
1257 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
1258 }
1259
1260 #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
1261 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
1262 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)1263 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
1264 {
1265 return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
1266 }
1267
1268 #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
1269 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
1270 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)1271 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
1272 {
1273 return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
1274 }
1275
1276 #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
1277
1278 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
1279 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff
1280 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0
CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)1281 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)
1282 {
1283 return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK;
1284 }
1285
1286 #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
1287
1288 #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
1289 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
1290 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)1291 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
1292 {
1293 return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
1294 }
1295
1296 #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
1297 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
1298 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)1299 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
1300 {
1301 return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
1302 }
1303
1304 #define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007
1305
1306 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
1307
1308 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
1309 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
1310 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)1311 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
1312 {
1313 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
1314 }
1315
1316 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
1317 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
1318 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)1319 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
1320 {
1321 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
1322 }
1323
1324 #define REG_CP_EVENT_WRITE_0 0x00000000
1325 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
1326 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0
CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)1327 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
1328 {
1329 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
1330 }
1331 #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
1332
1333 #define REG_CP_EVENT_WRITE_1 0x00000001
1334 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
1335 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)1336 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
1337 {
1338 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
1339 }
1340
1341 #define REG_CP_EVENT_WRITE_2 0x00000002
1342 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
1343 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)1344 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
1345 {
1346 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
1347 }
1348
1349 #define REG_CP_EVENT_WRITE_3 0x00000003
1350
1351 #define REG_CP_BLIT_0 0x00000000
1352 #define CP_BLIT_0_OP__MASK 0x0000000f
1353 #define CP_BLIT_0_OP__SHIFT 0
CP_BLIT_0_OP(enum cp_blit_cmd val)1354 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
1355 {
1356 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
1357 }
1358
1359 #define REG_CP_BLIT_1 0x00000001
1360 #define CP_BLIT_1_SRC_X1__MASK 0x00003fff
1361 #define CP_BLIT_1_SRC_X1__SHIFT 0
CP_BLIT_1_SRC_X1(uint32_t val)1362 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
1363 {
1364 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
1365 }
1366 #define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000
1367 #define CP_BLIT_1_SRC_Y1__SHIFT 16
CP_BLIT_1_SRC_Y1(uint32_t val)1368 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
1369 {
1370 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
1371 }
1372
1373 #define REG_CP_BLIT_2 0x00000002
1374 #define CP_BLIT_2_SRC_X2__MASK 0x00003fff
1375 #define CP_BLIT_2_SRC_X2__SHIFT 0
CP_BLIT_2_SRC_X2(uint32_t val)1376 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
1377 {
1378 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
1379 }
1380 #define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000
1381 #define CP_BLIT_2_SRC_Y2__SHIFT 16
CP_BLIT_2_SRC_Y2(uint32_t val)1382 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
1383 {
1384 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
1385 }
1386
1387 #define REG_CP_BLIT_3 0x00000003
1388 #define CP_BLIT_3_DST_X1__MASK 0x00003fff
1389 #define CP_BLIT_3_DST_X1__SHIFT 0
CP_BLIT_3_DST_X1(uint32_t val)1390 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
1391 {
1392 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
1393 }
1394 #define CP_BLIT_3_DST_Y1__MASK 0x3fff0000
1395 #define CP_BLIT_3_DST_Y1__SHIFT 16
CP_BLIT_3_DST_Y1(uint32_t val)1396 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
1397 {
1398 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
1399 }
1400
1401 #define REG_CP_BLIT_4 0x00000004
1402 #define CP_BLIT_4_DST_X2__MASK 0x00003fff
1403 #define CP_BLIT_4_DST_X2__SHIFT 0
CP_BLIT_4_DST_X2(uint32_t val)1404 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
1405 {
1406 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
1407 }
1408 #define CP_BLIT_4_DST_Y2__MASK 0x3fff0000
1409 #define CP_BLIT_4_DST_Y2__SHIFT 16
CP_BLIT_4_DST_Y2(uint32_t val)1410 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
1411 {
1412 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
1413 }
1414
1415 #define REG_CP_EXEC_CS_0 0x00000000
1416
1417 #define REG_CP_EXEC_CS_1 0x00000001
1418 #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
1419 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
CP_EXEC_CS_1_NGROUPS_X(uint32_t val)1420 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
1421 {
1422 return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
1423 }
1424
1425 #define REG_CP_EXEC_CS_2 0x00000002
1426 #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
1427 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)1428 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
1429 {
1430 return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
1431 }
1432
1433 #define REG_CP_EXEC_CS_3 0x00000003
1434 #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
1435 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)1436 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
1437 {
1438 return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
1439 }
1440
1441 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000
1442
1443
1444 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001
1445 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff
1446 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0
A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)1447 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
1448 {
1449 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
1450 }
1451
1452 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002
1453 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc
1454 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)1455 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
1456 {
1457 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
1458 }
1459 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000
1460 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)1461 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
1462 {
1463 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
1464 }
1465 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000
1466 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)1467 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
1468 {
1469 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
1470 }
1471
1472
1473 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001
1474 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
1475 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)1476 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
1477 {
1478 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
1479 }
1480
1481 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002
1482 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
1483 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)1484 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
1485 {
1486 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
1487 }
1488
1489 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003
1490 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
1491 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)1492 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
1493 {
1494 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
1495 }
1496 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
1497 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)1498 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
1499 {
1500 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
1501 }
1502 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
1503 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)1504 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
1505 {
1506 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
1507 }
1508
1509 #define REG_A2XX_CP_SET_MARKER_0 0x00000000
1510 #define A2XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f
1511 #define A2XX_CP_SET_MARKER_0_MARKER__SHIFT 0
A2XX_CP_SET_MARKER_0_MARKER(uint32_t val)1512 static inline uint32_t A2XX_CP_SET_MARKER_0_MARKER(uint32_t val)
1513 {
1514 return ((val) << A2XX_CP_SET_MARKER_0_MARKER__SHIFT) & A2XX_CP_SET_MARKER_0_MARKER__MASK;
1515 }
1516 #define A2XX_CP_SET_MARKER_0_MODE__MASK 0x0000000f
1517 #define A2XX_CP_SET_MARKER_0_MODE__SHIFT 0
A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)1518 static inline uint32_t A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)
1519 {
1520 return ((val) << A2XX_CP_SET_MARKER_0_MODE__SHIFT) & A2XX_CP_SET_MARKER_0_MODE__MASK;
1521 }
1522 #define A2XX_CP_SET_MARKER_0_IFPC 0x00000100
1523
REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0)1524 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1525
REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0)1526 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1527 #define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007
1528 #define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0
A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)1529 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
1530 {
1531 return ((val) << A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
1532 }
1533
REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0)1534 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
1535 #define A2XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff
1536 #define A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0
A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)1537 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
1538 {
1539 return ((val) << A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A2XX_CP_SET_PSEUDO_REG__1_LO__MASK;
1540 }
1541
REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0)1542 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
1543 #define A2XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff
1544 #define A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0
A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)1545 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
1546 {
1547 return ((val) << A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A2XX_CP_SET_PSEUDO_REG__2_HI__MASK;
1548 }
1549
1550 #define REG_A2XX_CP_REG_TEST_0 0x00000000
1551 #define A2XX_CP_REG_TEST_0_REG__MASK 0x00000fff
1552 #define A2XX_CP_REG_TEST_0_REG__SHIFT 0
A2XX_CP_REG_TEST_0_REG(uint32_t val)1553 static inline uint32_t A2XX_CP_REG_TEST_0_REG(uint32_t val)
1554 {
1555 return ((val) << A2XX_CP_REG_TEST_0_REG__SHIFT) & A2XX_CP_REG_TEST_0_REG__MASK;
1556 }
1557 #define A2XX_CP_REG_TEST_0_BIT__MASK 0x01f00000
1558 #define A2XX_CP_REG_TEST_0_BIT__SHIFT 20
A2XX_CP_REG_TEST_0_BIT(uint32_t val)1559 static inline uint32_t A2XX_CP_REG_TEST_0_BIT(uint32_t val)
1560 {
1561 return ((val) << A2XX_CP_REG_TEST_0_BIT__SHIFT) & A2XX_CP_REG_TEST_0_BIT__MASK;
1562 }
1563 #define A2XX_CP_REG_TEST_0_UNK25 0x02000000
1564
1565
1566 #endif /* ADRENO_PM4_XML */
1567