1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_VMX_CAPS_H 3 #define __KVM_X86_VMX_CAPS_H 4 5 #include <asm/vmx.h> 6 7 #include "lapic.h" 8 9 extern bool __read_mostly enable_vpid; 10 extern bool __read_mostly flexpriority_enabled; 11 extern bool __read_mostly enable_ept; 12 extern bool __read_mostly enable_unrestricted_guest; 13 extern bool __read_mostly enable_ept_ad_bits; 14 extern bool __read_mostly enable_pml; 15 extern int __read_mostly pt_mode; 16 17 #define PT_MODE_SYSTEM 0 18 #define PT_MODE_HOST_GUEST 1 19 20 struct nested_vmx_msrs { 21 /* 22 * We only store the "true" versions of the VMX capability MSRs. We 23 * generate the "non-true" versions by setting the must-be-1 bits 24 * according to the SDM. 25 */ 26 u32 procbased_ctls_low; 27 u32 procbased_ctls_high; 28 u32 secondary_ctls_low; 29 u32 secondary_ctls_high; 30 u32 pinbased_ctls_low; 31 u32 pinbased_ctls_high; 32 u32 exit_ctls_low; 33 u32 exit_ctls_high; 34 u32 entry_ctls_low; 35 u32 entry_ctls_high; 36 u32 misc_low; 37 u32 misc_high; 38 u32 ept_caps; 39 u32 vpid_caps; 40 u64 basic; 41 u64 cr0_fixed0; 42 u64 cr0_fixed1; 43 u64 cr4_fixed0; 44 u64 cr4_fixed1; 45 u64 vmcs_enum; 46 u64 vmfunc_controls; 47 }; 48 49 struct vmcs_config { 50 int size; 51 int order; 52 u32 basic_cap; 53 u32 revision_id; 54 u32 pin_based_exec_ctrl; 55 u32 cpu_based_exec_ctrl; 56 u32 cpu_based_2nd_exec_ctrl; 57 u32 vmexit_ctrl; 58 u32 vmentry_ctrl; 59 struct nested_vmx_msrs nested; 60 }; 61 extern struct vmcs_config vmcs_config; 62 63 struct vmx_capability { 64 u32 ept; 65 u32 vpid; 66 }; 67 extern struct vmx_capability vmx_capability; 68 cpu_has_vmx_basic_inout(void)69static inline bool cpu_has_vmx_basic_inout(void) 70 { 71 return (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT); 72 } 73 cpu_has_virtual_nmis(void)74static inline bool cpu_has_virtual_nmis(void) 75 { 76 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; 77 } 78 cpu_has_vmx_preemption_timer(void)79static inline bool cpu_has_vmx_preemption_timer(void) 80 { 81 return vmcs_config.pin_based_exec_ctrl & 82 PIN_BASED_VMX_PREEMPTION_TIMER; 83 } 84 cpu_has_vmx_posted_intr(void)85static inline bool cpu_has_vmx_posted_intr(void) 86 { 87 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) && 88 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; 89 } 90 cpu_has_load_ia32_efer(void)91static inline bool cpu_has_load_ia32_efer(void) 92 { 93 return (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_EFER) && 94 (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_EFER); 95 } 96 cpu_has_load_perf_global_ctrl(void)97static inline bool cpu_has_load_perf_global_ctrl(void) 98 { 99 return (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) && 100 (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 101 } 102 vmx_mpx_supported(void)103static inline bool vmx_mpx_supported(void) 104 { 105 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && 106 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); 107 } 108 cpu_has_vmx_tpr_shadow(void)109static inline bool cpu_has_vmx_tpr_shadow(void) 110 { 111 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; 112 } 113 cpu_need_tpr_shadow(struct kvm_vcpu * vcpu)114static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu) 115 { 116 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu); 117 } 118 cpu_has_vmx_msr_bitmap(void)119static inline bool cpu_has_vmx_msr_bitmap(void) 120 { 121 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; 122 } 123 cpu_has_secondary_exec_ctrls(void)124static inline bool cpu_has_secondary_exec_ctrls(void) 125 { 126 return vmcs_config.cpu_based_exec_ctrl & 127 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 128 } 129 cpu_has_vmx_virtualize_apic_accesses(void)130static inline bool cpu_has_vmx_virtualize_apic_accesses(void) 131 { 132 return vmcs_config.cpu_based_2nd_exec_ctrl & 133 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 134 } 135 cpu_has_vmx_ept(void)136static inline bool cpu_has_vmx_ept(void) 137 { 138 return vmcs_config.cpu_based_2nd_exec_ctrl & 139 SECONDARY_EXEC_ENABLE_EPT; 140 } 141 vmx_umip_emulated(void)142static inline bool vmx_umip_emulated(void) 143 { 144 return vmcs_config.cpu_based_2nd_exec_ctrl & 145 SECONDARY_EXEC_DESC; 146 } 147 cpu_has_vmx_rdtscp(void)148static inline bool cpu_has_vmx_rdtscp(void) 149 { 150 return vmcs_config.cpu_based_2nd_exec_ctrl & 151 SECONDARY_EXEC_RDTSCP; 152 } 153 cpu_has_vmx_virtualize_x2apic_mode(void)154static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) 155 { 156 return vmcs_config.cpu_based_2nd_exec_ctrl & 157 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 158 } 159 cpu_has_vmx_vpid(void)160static inline bool cpu_has_vmx_vpid(void) 161 { 162 return vmcs_config.cpu_based_2nd_exec_ctrl & 163 SECONDARY_EXEC_ENABLE_VPID; 164 } 165 cpu_has_vmx_wbinvd_exit(void)166static inline bool cpu_has_vmx_wbinvd_exit(void) 167 { 168 return vmcs_config.cpu_based_2nd_exec_ctrl & 169 SECONDARY_EXEC_WBINVD_EXITING; 170 } 171 cpu_has_vmx_unrestricted_guest(void)172static inline bool cpu_has_vmx_unrestricted_guest(void) 173 { 174 return vmcs_config.cpu_based_2nd_exec_ctrl & 175 SECONDARY_EXEC_UNRESTRICTED_GUEST; 176 } 177 cpu_has_vmx_apic_register_virt(void)178static inline bool cpu_has_vmx_apic_register_virt(void) 179 { 180 return vmcs_config.cpu_based_2nd_exec_ctrl & 181 SECONDARY_EXEC_APIC_REGISTER_VIRT; 182 } 183 cpu_has_vmx_virtual_intr_delivery(void)184static inline bool cpu_has_vmx_virtual_intr_delivery(void) 185 { 186 return vmcs_config.cpu_based_2nd_exec_ctrl & 187 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; 188 } 189 cpu_has_vmx_ple(void)190static inline bool cpu_has_vmx_ple(void) 191 { 192 return vmcs_config.cpu_based_2nd_exec_ctrl & 193 SECONDARY_EXEC_PAUSE_LOOP_EXITING; 194 } 195 vmx_rdrand_supported(void)196static inline bool vmx_rdrand_supported(void) 197 { 198 return vmcs_config.cpu_based_2nd_exec_ctrl & 199 SECONDARY_EXEC_RDRAND_EXITING; 200 } 201 cpu_has_vmx_invpcid(void)202static inline bool cpu_has_vmx_invpcid(void) 203 { 204 return vmcs_config.cpu_based_2nd_exec_ctrl & 205 SECONDARY_EXEC_ENABLE_INVPCID; 206 } 207 cpu_has_vmx_vmfunc(void)208static inline bool cpu_has_vmx_vmfunc(void) 209 { 210 return vmcs_config.cpu_based_2nd_exec_ctrl & 211 SECONDARY_EXEC_ENABLE_VMFUNC; 212 } 213 cpu_has_vmx_shadow_vmcs(void)214static inline bool cpu_has_vmx_shadow_vmcs(void) 215 { 216 u64 vmx_msr; 217 218 /* check if the cpu supports writing r/o exit information fields */ 219 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 220 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) 221 return false; 222 223 return vmcs_config.cpu_based_2nd_exec_ctrl & 224 SECONDARY_EXEC_SHADOW_VMCS; 225 } 226 cpu_has_vmx_encls_vmexit(void)227static inline bool cpu_has_vmx_encls_vmexit(void) 228 { 229 return vmcs_config.cpu_based_2nd_exec_ctrl & 230 SECONDARY_EXEC_ENCLS_EXITING; 231 } 232 vmx_rdseed_supported(void)233static inline bool vmx_rdseed_supported(void) 234 { 235 return vmcs_config.cpu_based_2nd_exec_ctrl & 236 SECONDARY_EXEC_RDSEED_EXITING; 237 } 238 cpu_has_vmx_pml(void)239static inline bool cpu_has_vmx_pml(void) 240 { 241 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML; 242 } 243 vmx_xsaves_supported(void)244static inline bool vmx_xsaves_supported(void) 245 { 246 return vmcs_config.cpu_based_2nd_exec_ctrl & 247 SECONDARY_EXEC_XSAVES; 248 } 249 vmx_waitpkg_supported(void)250static inline bool vmx_waitpkg_supported(void) 251 { 252 return vmcs_config.cpu_based_2nd_exec_ctrl & 253 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 254 } 255 cpu_has_vmx_tsc_scaling(void)256static inline bool cpu_has_vmx_tsc_scaling(void) 257 { 258 return vmcs_config.cpu_based_2nd_exec_ctrl & 259 SECONDARY_EXEC_TSC_SCALING; 260 } 261 cpu_has_vmx_apicv(void)262static inline bool cpu_has_vmx_apicv(void) 263 { 264 return cpu_has_vmx_apic_register_virt() && 265 cpu_has_vmx_virtual_intr_delivery() && 266 cpu_has_vmx_posted_intr(); 267 } 268 cpu_has_vmx_flexpriority(void)269static inline bool cpu_has_vmx_flexpriority(void) 270 { 271 return cpu_has_vmx_tpr_shadow() && 272 cpu_has_vmx_virtualize_apic_accesses(); 273 } 274 cpu_has_vmx_ept_execute_only(void)275static inline bool cpu_has_vmx_ept_execute_only(void) 276 { 277 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; 278 } 279 cpu_has_vmx_ept_4levels(void)280static inline bool cpu_has_vmx_ept_4levels(void) 281 { 282 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; 283 } 284 cpu_has_vmx_ept_5levels(void)285static inline bool cpu_has_vmx_ept_5levels(void) 286 { 287 return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT; 288 } 289 cpu_has_vmx_ept_mt_wb(void)290static inline bool cpu_has_vmx_ept_mt_wb(void) 291 { 292 return vmx_capability.ept & VMX_EPTP_WB_BIT; 293 } 294 cpu_has_vmx_ept_2m_page(void)295static inline bool cpu_has_vmx_ept_2m_page(void) 296 { 297 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; 298 } 299 cpu_has_vmx_ept_1g_page(void)300static inline bool cpu_has_vmx_ept_1g_page(void) 301 { 302 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; 303 } 304 cpu_has_vmx_ept_ad_bits(void)305static inline bool cpu_has_vmx_ept_ad_bits(void) 306 { 307 return vmx_capability.ept & VMX_EPT_AD_BIT; 308 } 309 cpu_has_vmx_invept_context(void)310static inline bool cpu_has_vmx_invept_context(void) 311 { 312 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; 313 } 314 cpu_has_vmx_invept_global(void)315static inline bool cpu_has_vmx_invept_global(void) 316 { 317 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; 318 } 319 cpu_has_vmx_invvpid(void)320static inline bool cpu_has_vmx_invvpid(void) 321 { 322 return vmx_capability.vpid & VMX_VPID_INVVPID_BIT; 323 } 324 cpu_has_vmx_invvpid_individual_addr(void)325static inline bool cpu_has_vmx_invvpid_individual_addr(void) 326 { 327 return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT; 328 } 329 cpu_has_vmx_invvpid_single(void)330static inline bool cpu_has_vmx_invvpid_single(void) 331 { 332 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; 333 } 334 cpu_has_vmx_invvpid_global(void)335static inline bool cpu_has_vmx_invvpid_global(void) 336 { 337 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; 338 } 339 cpu_has_vmx_intel_pt(void)340static inline bool cpu_has_vmx_intel_pt(void) 341 { 342 u64 vmx_msr; 343 344 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 345 return (vmx_msr & MSR_IA32_VMX_MISC_INTEL_PT) && 346 (vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_PT_USE_GPA) && 347 (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_IA32_RTIT_CTL) && 348 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_RTIT_CTL); 349 } 350 351 #endif /* __KVM_X86_VMX_CAPS_H */ 352