1 /*
2 * This file is part of the Chelsio T6 Crypto driver for Linux.
3 *
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 *
34 */
35
36 #ifndef __CHCR_CRYPTO_H__
37 #define __CHCR_CRYPTO_H__
38
39 #define GHASH_BLOCK_SIZE 16
40 #define GHASH_DIGEST_SIZE 16
41
42 #define CCM_B0_SIZE 16
43 #define CCM_AAD_FIELD_SIZE 2
44 // 511 - 16(For IV)
45 #define T6_MAX_AAD_SIZE 495
46
47
48 /* Define following if h/w is not dropping the AAD and IV data before
49 * giving the processed data
50 */
51
52 #define CHCR_CRA_PRIORITY 500
53 #define CHCR_AEAD_PRIORITY 6000
54 #define CHCR_AES_MAX_KEY_LEN (2 * (AES_MAX_KEY_SIZE)) /* consider xts */
55 #define CHCR_MAX_CRYPTO_IV_LEN 16 /* AES IV len */
56
57 #define CHCR_MAX_AUTHENC_AES_KEY_LEN 32 /* max aes key length*/
58 #define CHCR_MAX_AUTHENC_SHA_KEY_LEN 128 /* max sha key length*/
59
60 #define CHCR_GIVENCRYPT_OP 2
61 /* CPL/SCMD parameters */
62
63 #define CHCR_ENCRYPT_OP 0
64 #define CHCR_DECRYPT_OP 1
65
66 #define CHCR_SCMD_SEQ_NO_CTRL_32BIT 1
67 #define CHCR_SCMD_SEQ_NO_CTRL_48BIT 2
68 #define CHCR_SCMD_SEQ_NO_CTRL_64BIT 3
69
70 #define CHCR_SCMD_PROTO_VERSION_GENERIC 4
71
72 #define CHCR_SCMD_AUTH_CTRL_AUTH_CIPHER 0
73 #define CHCR_SCMD_AUTH_CTRL_CIPHER_AUTH 1
74
75 #define CHCR_SCMD_CIPHER_MODE_NOP 0
76 #define CHCR_SCMD_CIPHER_MODE_AES_CBC 1
77 #define CHCR_SCMD_CIPHER_MODE_AES_GCM 2
78 #define CHCR_SCMD_CIPHER_MODE_AES_CTR 3
79 #define CHCR_SCMD_CIPHER_MODE_GENERIC_AES 4
80 #define CHCR_SCMD_CIPHER_MODE_AES_XTS 6
81 #define CHCR_SCMD_CIPHER_MODE_AES_CCM 7
82
83 #define CHCR_SCMD_AUTH_MODE_NOP 0
84 #define CHCR_SCMD_AUTH_MODE_SHA1 1
85 #define CHCR_SCMD_AUTH_MODE_SHA224 2
86 #define CHCR_SCMD_AUTH_MODE_SHA256 3
87 #define CHCR_SCMD_AUTH_MODE_GHASH 4
88 #define CHCR_SCMD_AUTH_MODE_SHA512_224 5
89 #define CHCR_SCMD_AUTH_MODE_SHA512_256 6
90 #define CHCR_SCMD_AUTH_MODE_SHA512_384 7
91 #define CHCR_SCMD_AUTH_MODE_SHA512_512 8
92 #define CHCR_SCMD_AUTH_MODE_CBCMAC 9
93 #define CHCR_SCMD_AUTH_MODE_CMAC 10
94
95 #define CHCR_SCMD_HMAC_CTRL_NOP 0
96 #define CHCR_SCMD_HMAC_CTRL_NO_TRUNC 1
97 #define CHCR_SCMD_HMAC_CTRL_TRUNC_RFC4366 2
98 #define CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT 3
99 #define CHCR_SCMD_HMAC_CTRL_PL1 4
100 #define CHCR_SCMD_HMAC_CTRL_PL2 5
101 #define CHCR_SCMD_HMAC_CTRL_PL3 6
102 #define CHCR_SCMD_HMAC_CTRL_DIV2 7
103 #define VERIFY_HW 0
104 #define VERIFY_SW 1
105
106 #define CHCR_SCMD_IVGEN_CTRL_HW 0
107 #define CHCR_SCMD_IVGEN_CTRL_SW 1
108 /* This are not really mac key size. They are intermediate values
109 * of sha engine and its size
110 */
111 #define CHCR_KEYCTX_MAC_KEY_SIZE_128 0
112 #define CHCR_KEYCTX_MAC_KEY_SIZE_160 1
113 #define CHCR_KEYCTX_MAC_KEY_SIZE_192 2
114 #define CHCR_KEYCTX_MAC_KEY_SIZE_256 3
115 #define CHCR_KEYCTX_MAC_KEY_SIZE_512 4
116 #define CHCR_KEYCTX_CIPHER_KEY_SIZE_128 0
117 #define CHCR_KEYCTX_CIPHER_KEY_SIZE_192 1
118 #define CHCR_KEYCTX_CIPHER_KEY_SIZE_256 2
119 #define CHCR_KEYCTX_NO_KEY 15
120
121 #define CHCR_CPL_FW4_PLD_IV_OFFSET (5 * 64) /* bytes. flt #5 and #6 */
122 #define CHCR_CPL_FW4_PLD_HASH_RESULT_OFFSET (7 * 64) /* bytes. flt #7 */
123 #define CHCR_CPL_FW4_PLD_DATA_SIZE (4 * 64) /* bytes. flt #4 to #7 */
124
125 #define KEY_CONTEXT_HDR_SALT_AND_PAD 16
126 #define flits_to_bytes(x) (x * 8)
127
128 #define IV_NOP 0
129 #define IV_IMMEDIATE 1
130 #define IV_DSGL 2
131
132 #define AEAD_H_SIZE 16
133
134 #define CRYPTO_ALG_SUB_TYPE_MASK 0x0f000000
135 #define CRYPTO_ALG_SUB_TYPE_HASH_HMAC 0x01000000
136 #define CRYPTO_ALG_SUB_TYPE_AEAD_RFC4106 0x02000000
137 #define CRYPTO_ALG_SUB_TYPE_AEAD_GCM 0x03000000
138 #define CRYPTO_ALG_SUB_TYPE_CBC_SHA 0x04000000
139 #define CRYPTO_ALG_SUB_TYPE_AEAD_CCM 0x05000000
140 #define CRYPTO_ALG_SUB_TYPE_AEAD_RFC4309 0x06000000
141 #define CRYPTO_ALG_SUB_TYPE_CBC_NULL 0x07000000
142 #define CRYPTO_ALG_SUB_TYPE_CTR 0x08000000
143 #define CRYPTO_ALG_SUB_TYPE_CTR_RFC3686 0x09000000
144 #define CRYPTO_ALG_SUB_TYPE_XTS 0x0a000000
145 #define CRYPTO_ALG_SUB_TYPE_CBC 0x0b000000
146 #define CRYPTO_ALG_SUB_TYPE_CTR_SHA 0x0c000000
147 #define CRYPTO_ALG_SUB_TYPE_CTR_NULL 0x0d000000
148 #define CRYPTO_ALG_TYPE_HMAC (CRYPTO_ALG_TYPE_AHASH |\
149 CRYPTO_ALG_SUB_TYPE_HASH_HMAC)
150
151 #define MAX_SCRATCH_PAD_SIZE 32
152
153 #define CHCR_HASH_MAX_BLOCK_SIZE_64 64
154 #define CHCR_HASH_MAX_BLOCK_SIZE_128 128
155 #define CHCR_SRC_SG_SIZE (0x10000 - sizeof(int))
156 #define CHCR_DST_SG_SIZE 2048
157
a_ctx(struct crypto_aead * tfm)158 static inline struct chcr_context *a_ctx(struct crypto_aead *tfm)
159 {
160 return crypto_aead_ctx(tfm);
161 }
162
c_ctx(struct crypto_ablkcipher * tfm)163 static inline struct chcr_context *c_ctx(struct crypto_ablkcipher *tfm)
164 {
165 return crypto_ablkcipher_ctx(tfm);
166 }
167
h_ctx(struct crypto_ahash * tfm)168 static inline struct chcr_context *h_ctx(struct crypto_ahash *tfm)
169 {
170 return crypto_tfm_ctx(crypto_ahash_tfm(tfm));
171 }
172
173 struct ablk_ctx {
174 struct crypto_sync_skcipher *sw_cipher;
175 __be32 key_ctx_hdr;
176 unsigned int enckey_len;
177 unsigned char ciph_mode;
178 u8 key[CHCR_AES_MAX_KEY_LEN];
179 u8 nonce[4];
180 u8 rrkey[AES_MAX_KEY_SIZE];
181 };
182 struct chcr_aead_reqctx {
183 struct sk_buff *skb;
184 dma_addr_t iv_dma;
185 dma_addr_t b0_dma;
186 unsigned int b0_len;
187 unsigned int op;
188 u16 imm;
189 u16 verify;
190 u8 iv[CHCR_MAX_CRYPTO_IV_LEN + MAX_SCRATCH_PAD_SIZE];
191 u8 *scratch_pad;
192 };
193
194 struct ulptx_walk {
195 struct ulptx_sgl *sgl;
196 unsigned int nents;
197 unsigned int pair_idx;
198 unsigned int last_sg_len;
199 struct scatterlist *last_sg;
200 struct ulptx_sge_pair *pair;
201
202 };
203
204 struct dsgl_walk {
205 unsigned int nents;
206 unsigned int last_sg_len;
207 struct scatterlist *last_sg;
208 struct cpl_rx_phys_dsgl *dsgl;
209 struct phys_sge_pairs *to;
210 };
211
212 struct chcr_gcm_ctx {
213 u8 ghash_h[AEAD_H_SIZE];
214 };
215
216 struct chcr_authenc_ctx {
217 u8 dec_rrkey[AES_MAX_KEY_SIZE];
218 u8 h_iopad[2 * CHCR_HASH_MAX_DIGEST_SIZE];
219 unsigned char auth_mode;
220 };
221
222 struct __aead_ctx {
223 struct chcr_gcm_ctx gcm[0];
224 struct chcr_authenc_ctx authenc[0];
225 };
226
227 struct chcr_aead_ctx {
228 __be32 key_ctx_hdr;
229 unsigned int enckey_len;
230 struct crypto_aead *sw_cipher;
231 u8 salt[MAX_SALT];
232 u8 key[CHCR_AES_MAX_KEY_LEN];
233 u8 nonce[4];
234 u16 hmac_ctrl;
235 u16 mayverify;
236 struct __aead_ctx ctx[0];
237 };
238
239 struct hmac_ctx {
240 struct crypto_shash *base_hash;
241 u8 ipad[CHCR_HASH_MAX_BLOCK_SIZE_128];
242 u8 opad[CHCR_HASH_MAX_BLOCK_SIZE_128];
243 };
244
245 struct __crypto_ctx {
246 struct hmac_ctx hmacctx[0];
247 struct ablk_ctx ablkctx[0];
248 struct chcr_aead_ctx aeadctx[0];
249 };
250
251 struct chcr_context {
252 struct chcr_dev *dev;
253 unsigned char tx_qidx;
254 unsigned char rx_qidx;
255 unsigned char tx_chan_id;
256 unsigned char pci_chan_id;
257 struct __crypto_ctx crypto_ctx[0];
258 };
259
260 struct chcr_hctx_per_wr {
261 struct scatterlist *srcsg;
262 struct sk_buff *skb;
263 dma_addr_t dma_addr;
264 u32 dma_len;
265 unsigned int src_ofst;
266 unsigned int processed;
267 u32 result;
268 u8 is_sg_map;
269 u8 imm;
270 /*Final callback called. Driver cannot rely on nbytes to decide
271 * final call
272 */
273 u8 isfinal;
274 };
275
276 struct chcr_ahash_req_ctx {
277 struct chcr_hctx_per_wr hctx_wr;
278 u8 *reqbfr;
279 u8 *skbfr;
280 /* SKB which is being sent to the hardware for processing */
281 u64 data_len; /* Data len till time */
282 u8 reqlen;
283 u8 partial_hash[CHCR_HASH_MAX_DIGEST_SIZE];
284 u8 bfr1[CHCR_HASH_MAX_BLOCK_SIZE_128];
285 u8 bfr2[CHCR_HASH_MAX_BLOCK_SIZE_128];
286 };
287
288 struct chcr_blkcipher_req_ctx {
289 struct sk_buff *skb;
290 struct scatterlist *dstsg;
291 unsigned int processed;
292 unsigned int last_req_len;
293 struct scatterlist *srcsg;
294 unsigned int src_ofst;
295 unsigned int dst_ofst;
296 unsigned int op;
297 u16 imm;
298 u8 iv[CHCR_MAX_CRYPTO_IV_LEN];
299 };
300
301 struct chcr_alg_template {
302 u32 type;
303 u32 is_registered;
304 union {
305 struct crypto_alg crypto;
306 struct ahash_alg hash;
307 struct aead_alg aead;
308 } alg;
309 };
310
311 typedef struct sk_buff *(*create_wr_t)(struct aead_request *req,
312 unsigned short qid,
313 int size);
314
315 void chcr_verify_tag(struct aead_request *req, u8 *input, int *err);
316 int chcr_aead_dma_map(struct device *dev, struct aead_request *req,
317 unsigned short op_type);
318 void chcr_aead_dma_unmap(struct device *dev, struct aead_request *req,
319 unsigned short op_type);
320 void chcr_add_aead_dst_ent(struct aead_request *req,
321 struct cpl_rx_phys_dsgl *phys_cpl,
322 unsigned short qid);
323 void chcr_add_aead_src_ent(struct aead_request *req, struct ulptx_sgl *ulptx);
324 void chcr_add_cipher_src_ent(struct ablkcipher_request *req,
325 void *ulptx,
326 struct cipher_wr_param *wrparam);
327 int chcr_cipher_dma_map(struct device *dev, struct ablkcipher_request *req);
328 void chcr_cipher_dma_unmap(struct device *dev, struct ablkcipher_request *req);
329 void chcr_add_cipher_dst_ent(struct ablkcipher_request *req,
330 struct cpl_rx_phys_dsgl *phys_cpl,
331 struct cipher_wr_param *wrparam,
332 unsigned short qid);
333 int sg_nents_len_skip(struct scatterlist *sg, u64 len, u64 skip);
334 void chcr_add_hash_src_ent(struct ahash_request *req, struct ulptx_sgl *ulptx,
335 struct hash_wr_param *param);
336 int chcr_hash_dma_map(struct device *dev, struct ahash_request *req);
337 void chcr_hash_dma_unmap(struct device *dev, struct ahash_request *req);
338 void chcr_aead_common_exit(struct aead_request *req);
339 #endif /* __CHCR_CRYPTO_H__ */
340