1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Code specific to PKUnity SoC and UniCore ISA 4 * 5 * Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn> 6 * Copyright (C) 2001-2011 Guan Xuetao 7 */ 8 #ifndef _I8042_UNICORE32_H 9 #define _I8042_UNICORE32_H 10 11 #include <mach/hardware.h> 12 13 /* 14 * Names. 15 */ 16 #define I8042_KBD_PHYS_DESC "isa0060/serio0" 17 #define I8042_AUX_PHYS_DESC "isa0060/serio1" 18 #define I8042_MUX_PHYS_DESC "isa0060/serio%d" 19 20 /* 21 * IRQs. 22 */ 23 #define I8042_KBD_IRQ IRQ_PS2_KBD 24 #define I8042_AUX_IRQ IRQ_PS2_AUX 25 26 /* 27 * Register numbers. 28 */ 29 #define I8042_COMMAND_REG PS2_COMMAND 30 #define I8042_STATUS_REG PS2_STATUS 31 #define I8042_DATA_REG PS2_DATA 32 33 #define I8042_REGION_START (resource_size_t)(PS2_DATA) 34 #define I8042_REGION_SIZE (resource_size_t)(16) 35 i8042_read_data(void)36static inline int i8042_read_data(void) 37 { 38 return readb(I8042_DATA_REG); 39 } 40 i8042_read_status(void)41static inline int i8042_read_status(void) 42 { 43 return readb(I8042_STATUS_REG); 44 } 45 i8042_write_data(int val)46static inline void i8042_write_data(int val) 47 { 48 writeb(val, I8042_DATA_REG); 49 } 50 i8042_write_command(int val)51static inline void i8042_write_command(int val) 52 { 53 writeb(val, I8042_COMMAND_REG); 54 } 55 i8042_platform_init(void)56static inline int i8042_platform_init(void) 57 { 58 if (!request_mem_region(I8042_REGION_START, I8042_REGION_SIZE, "i8042")) 59 return -EBUSY; 60 61 i8042_reset = I8042_RESET_ALWAYS; 62 return 0; 63 } 64 i8042_platform_exit(void)65static inline void i8042_platform_exit(void) 66 { 67 release_mem_region(I8042_REGION_START, I8042_REGION_SIZE); 68 } 69 70 #endif /* _I8042_UNICORE32_H */ 71