1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH Pin Function Controller GPIO driver.
4 *
5 * Copyright (C) 2008 Magnus Damm
6 * Copyright (C) 2009 - 2012 Paul Mundt
7 */
8
9 #include <linux/device.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/pinctrl/consumer.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16
17 #include "core.h"
18
19 struct sh_pfc_gpio_data_reg {
20 const struct pinmux_data_reg *info;
21 u32 shadow;
22 };
23
24 struct sh_pfc_gpio_pin {
25 u8 dbit;
26 u8 dreg;
27 };
28
29 struct sh_pfc_chip {
30 struct sh_pfc *pfc;
31 struct gpio_chip gpio_chip;
32
33 struct sh_pfc_window *mem;
34 struct sh_pfc_gpio_data_reg *regs;
35 struct sh_pfc_gpio_pin *pins;
36 };
37
gpio_to_pfc(struct gpio_chip * gc)38 static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
39 {
40 struct sh_pfc_chip *chip = gpiochip_get_data(gc);
41 return chip->pfc;
42 }
43
gpio_get_data_reg(struct sh_pfc_chip * chip,unsigned int offset,struct sh_pfc_gpio_data_reg ** reg,unsigned int * bit)44 static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
45 struct sh_pfc_gpio_data_reg **reg,
46 unsigned int *bit)
47 {
48 int idx = sh_pfc_get_pin_index(chip->pfc, offset);
49 struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
50
51 *reg = &chip->regs[gpio_pin->dreg];
52 *bit = gpio_pin->dbit;
53 }
54
gpio_read_data_reg(struct sh_pfc_chip * chip,const struct pinmux_data_reg * dreg)55 static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
56 const struct pinmux_data_reg *dreg)
57 {
58 phys_addr_t address = dreg->reg;
59 void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
60
61 return sh_pfc_read_raw_reg(mem, dreg->reg_width);
62 }
63
gpio_write_data_reg(struct sh_pfc_chip * chip,const struct pinmux_data_reg * dreg,u32 value)64 static void gpio_write_data_reg(struct sh_pfc_chip *chip,
65 const struct pinmux_data_reg *dreg, u32 value)
66 {
67 phys_addr_t address = dreg->reg;
68 void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
69
70 sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
71 }
72
gpio_setup_data_reg(struct sh_pfc_chip * chip,unsigned idx)73 static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
74 {
75 struct sh_pfc *pfc = chip->pfc;
76 struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
77 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
78 const struct pinmux_data_reg *dreg;
79 unsigned int bit;
80 unsigned int i;
81
82 for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
83 for (bit = 0; bit < dreg->reg_width; bit++) {
84 if (dreg->enum_ids[bit] == pin->enum_id) {
85 gpio_pin->dreg = i;
86 gpio_pin->dbit = bit;
87 return;
88 }
89 }
90 }
91
92 BUG();
93 }
94
gpio_setup_data_regs(struct sh_pfc_chip * chip)95 static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
96 {
97 struct sh_pfc *pfc = chip->pfc;
98 const struct pinmux_data_reg *dreg;
99 unsigned int i;
100
101 /* Count the number of data registers, allocate memory and initialize
102 * them.
103 */
104 for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
105 ;
106
107 chip->regs = devm_kcalloc(pfc->dev, i, sizeof(*chip->regs),
108 GFP_KERNEL);
109 if (chip->regs == NULL)
110 return -ENOMEM;
111
112 for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
113 chip->regs[i].info = dreg;
114 chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
115 }
116
117 for (i = 0; i < pfc->info->nr_pins; i++) {
118 if (pfc->info->pins[i].enum_id == 0)
119 continue;
120
121 gpio_setup_data_reg(chip, i);
122 }
123
124 return 0;
125 }
126
127 /* -----------------------------------------------------------------------------
128 * Pin GPIOs
129 */
130
gpio_pin_request(struct gpio_chip * gc,unsigned offset)131 static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
132 {
133 struct sh_pfc *pfc = gpio_to_pfc(gc);
134 int idx = sh_pfc_get_pin_index(pfc, offset);
135
136 if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
137 return -EINVAL;
138
139 return pinctrl_gpio_request(offset);
140 }
141
gpio_pin_free(struct gpio_chip * gc,unsigned offset)142 static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
143 {
144 return pinctrl_gpio_free(offset);
145 }
146
gpio_pin_set_value(struct sh_pfc_chip * chip,unsigned offset,int value)147 static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
148 int value)
149 {
150 struct sh_pfc_gpio_data_reg *reg;
151 unsigned int bit;
152 unsigned int pos;
153
154 gpio_get_data_reg(chip, offset, ®, &bit);
155
156 pos = reg->info->reg_width - (bit + 1);
157
158 if (value)
159 reg->shadow |= BIT(pos);
160 else
161 reg->shadow &= ~BIT(pos);
162
163 gpio_write_data_reg(chip, reg->info, reg->shadow);
164 }
165
gpio_pin_direction_input(struct gpio_chip * gc,unsigned offset)166 static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
167 {
168 return pinctrl_gpio_direction_input(offset);
169 }
170
gpio_pin_direction_output(struct gpio_chip * gc,unsigned offset,int value)171 static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
172 int value)
173 {
174 gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
175
176 return pinctrl_gpio_direction_output(offset);
177 }
178
gpio_pin_get(struct gpio_chip * gc,unsigned offset)179 static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
180 {
181 struct sh_pfc_chip *chip = gpiochip_get_data(gc);
182 struct sh_pfc_gpio_data_reg *reg;
183 unsigned int bit;
184 unsigned int pos;
185
186 gpio_get_data_reg(chip, offset, ®, &bit);
187
188 pos = reg->info->reg_width - (bit + 1);
189
190 return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
191 }
192
gpio_pin_set(struct gpio_chip * gc,unsigned offset,int value)193 static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
194 {
195 gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
196 }
197
gpio_pin_to_irq(struct gpio_chip * gc,unsigned offset)198 static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
199 {
200 struct sh_pfc *pfc = gpio_to_pfc(gc);
201 unsigned int i, k;
202
203 for (i = 0; i < pfc->info->gpio_irq_size; i++) {
204 const short *gpios = pfc->info->gpio_irq[i].gpios;
205
206 for (k = 0; gpios[k] >= 0; k++) {
207 if (gpios[k] == offset)
208 goto found;
209 }
210 }
211
212 return 0;
213
214 found:
215 return pfc->irqs[i];
216 }
217
gpio_pin_setup(struct sh_pfc_chip * chip)218 static int gpio_pin_setup(struct sh_pfc_chip *chip)
219 {
220 struct sh_pfc *pfc = chip->pfc;
221 struct gpio_chip *gc = &chip->gpio_chip;
222 int ret;
223
224 chip->pins = devm_kcalloc(pfc->dev,
225 pfc->info->nr_pins, sizeof(*chip->pins),
226 GFP_KERNEL);
227 if (chip->pins == NULL)
228 return -ENOMEM;
229
230 ret = gpio_setup_data_regs(chip);
231 if (ret < 0)
232 return ret;
233
234 gc->request = gpio_pin_request;
235 gc->free = gpio_pin_free;
236 gc->direction_input = gpio_pin_direction_input;
237 gc->get = gpio_pin_get;
238 gc->direction_output = gpio_pin_direction_output;
239 gc->set = gpio_pin_set;
240 gc->to_irq = gpio_pin_to_irq;
241
242 gc->label = pfc->info->name;
243 gc->parent = pfc->dev;
244 gc->owner = THIS_MODULE;
245 gc->base = 0;
246 gc->ngpio = pfc->nr_gpio_pins;
247
248 return 0;
249 }
250
251 /* -----------------------------------------------------------------------------
252 * Function GPIOs
253 */
254
255 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
gpio_function_request(struct gpio_chip * gc,unsigned offset)256 static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
257 {
258 struct sh_pfc *pfc = gpio_to_pfc(gc);
259 unsigned int mark = pfc->info->func_gpios[offset].enum_id;
260 unsigned long flags;
261 int ret;
262
263 dev_notice_once(pfc->dev,
264 "Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
265
266 if (mark == 0)
267 return -EINVAL;
268
269 spin_lock_irqsave(&pfc->lock, flags);
270 ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
271 spin_unlock_irqrestore(&pfc->lock, flags);
272
273 return ret;
274 }
275
gpio_function_setup(struct sh_pfc_chip * chip)276 static int gpio_function_setup(struct sh_pfc_chip *chip)
277 {
278 struct sh_pfc *pfc = chip->pfc;
279 struct gpio_chip *gc = &chip->gpio_chip;
280
281 gc->request = gpio_function_request;
282
283 gc->label = pfc->info->name;
284 gc->owner = THIS_MODULE;
285 gc->base = pfc->nr_gpio_pins;
286 gc->ngpio = pfc->info->nr_func_gpios;
287
288 return 0;
289 }
290 #endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
291
292 /* -----------------------------------------------------------------------------
293 * Register/unregister
294 */
295
296 static struct sh_pfc_chip *
sh_pfc_add_gpiochip(struct sh_pfc * pfc,int (* setup)(struct sh_pfc_chip *),struct sh_pfc_window * mem)297 sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
298 struct sh_pfc_window *mem)
299 {
300 struct sh_pfc_chip *chip;
301 int ret;
302
303 chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
304 if (unlikely(!chip))
305 return ERR_PTR(-ENOMEM);
306
307 chip->mem = mem;
308 chip->pfc = pfc;
309
310 ret = setup(chip);
311 if (ret < 0)
312 return ERR_PTR(ret);
313
314 ret = devm_gpiochip_add_data(pfc->dev, &chip->gpio_chip, chip);
315 if (unlikely(ret < 0))
316 return ERR_PTR(ret);
317
318 dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
319 chip->gpio_chip.label, chip->gpio_chip.base,
320 chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
321
322 return chip;
323 }
324
sh_pfc_register_gpiochip(struct sh_pfc * pfc)325 int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
326 {
327 struct sh_pfc_chip *chip;
328 phys_addr_t address;
329 unsigned int i;
330
331 if (pfc->info->data_regs == NULL)
332 return 0;
333
334 /* Find the memory window that contain the GPIO registers. Boards that
335 * register a separate GPIO device will not supply a memory resource
336 * that covers the data registers. In that case don't try to handle
337 * GPIOs.
338 */
339 address = pfc->info->data_regs[0].reg;
340 for (i = 0; i < pfc->num_windows; ++i) {
341 struct sh_pfc_window *window = &pfc->windows[i];
342
343 if (address >= window->phys &&
344 address < window->phys + window->size)
345 break;
346 }
347
348 if (i == pfc->num_windows)
349 return 0;
350
351 /* If we have IRQ resources make sure their number is correct. */
352 if (pfc->num_irqs != pfc->info->gpio_irq_size) {
353 dev_err(pfc->dev, "invalid number of IRQ resources\n");
354 return -EINVAL;
355 }
356
357 /* Register the real GPIOs chip. */
358 chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
359 if (IS_ERR(chip))
360 return PTR_ERR(chip);
361
362 pfc->gpio = chip;
363
364 if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
365 return 0;
366
367 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
368 /*
369 * Register the GPIO to pin mappings. As pins with GPIO ports
370 * must come first in the ranges, skip the pins without GPIO
371 * ports by stopping at the first range that contains such a
372 * pin.
373 */
374 for (i = 0; i < pfc->nr_ranges; ++i) {
375 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
376 int ret;
377
378 if (range->start >= pfc->nr_gpio_pins)
379 break;
380
381 ret = gpiochip_add_pin_range(&chip->gpio_chip,
382 dev_name(pfc->dev), range->start, range->start,
383 range->end - range->start + 1);
384 if (ret < 0)
385 return ret;
386 }
387
388 /* Register the function GPIOs chip. */
389 if (pfc->info->nr_func_gpios == 0)
390 return 0;
391
392 chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
393 if (IS_ERR(chip))
394 return PTR_ERR(chip);
395 #endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
396
397 return 0;
398 }
399