| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7723.c | 109 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator
117 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
146 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
151 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
168 [HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0),
173 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0),
204 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7757.c | 60 enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR }; enumerator
71 [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
109 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-shx3.c | 59 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR }; enumerator
69 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
110 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7724.c | 148 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; enumerator
155 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
208 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
212 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
248 [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0),
269 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7785.c | 63 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, enumerator
75 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
127 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7366.c | 105 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator
114 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
145 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
193 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7786.c | 65 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; enumerator
75 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
135 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7722.c | 111 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator
116 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
179 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7343.c | 102 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator
111 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
195 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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