Searched refs:DIV4_U (Results 1 – 5 of 5) sorted by relevance
| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7722.c | 111 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator
115 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
142 [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
178 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
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| D | clock-sh7785.c | 63 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, enumerator
76 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
128 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
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| D | clock-sh7343.c | 102 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator
110 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
142 [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
194 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
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| D | clock-sh7366.c | 105 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator
113 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
192 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
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| D | clock-sh7723.c | 109 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator
116 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
203 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
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