Searched refs:E1 (Results 1 – 14 of 14) sorted by relevance
| /arch/x86/crypto/ |
| D | sha1_ni_asm.S | 69 #define E1 %xmm2 macro
124 movdqa ABCD, E1
130 sha1nexte MSG1, E1
132 sha1rnds4 $0, E1, ABCD
139 movdqa ABCD, E1
147 sha1nexte MSG3, E1
150 sha1rnds4 $0, E1, ABCD
156 movdqa ABCD, E1
163 sha1nexte MSG1, E1
166 sha1rnds4 $1, E1, ABCD
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| /arch/m68k/fpsp040/ |
| D | skeleton.S | 68 bclrb #E1,E_BYTE(%a6)
85 | otherwise clear the E1 exception. The frestore is not really
86 | necessary for E1 exceptions.
89 | bug, if an E1 snan, ovfl, or unfl occurred, and the process was
93 | fix is to check for E1, and the existence of one of snan, ovfl,
108 btstb #E1,E_BYTE(%a6) |test for E1 set
158 bclrb #E1,E_BYTE(%a6)
184 bclrb #E1,E_BYTE(%a6)
210 bclrb #E1,E_BYTE(%a6)
233 bclrb #E1,E_BYTE(%a6) |snan is always an E1 exception
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| D | gen_except.S | 168 | exception is to set the E1/E3 byte and clr the U flag.
169 | commonE1 does this for E1 exceptions, which are snan,
171 | are inex2 and inex1, and also clears the E1 exception bit
175 bsetb #E1,E_BYTE(%a6) |set E1 flag
183 bclrb #E1,E_BYTE(%a6) |clr E1 from unimp
192 bclrb #E1,E_BYTE(%a6) |clr E1 flag
268 bsetb #E1,E_BYTE(%a6) |set E1 exception flag
301 bclrb #E1,E_BYTE(%a6) |make sure E1 is clear
349 | We need to set the nmcexc bits if the exception is E1. Otherwise,
358 | btst.b #E1,E_BYTE(%a1)
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| D | fpsp.h | 172 .set CMDREG1B,LV-36 | cmd reg for E1 exceptions (2 bytes)
189 .set E_BYTE,LV-28 | holds E1 and E3 bits (1 byte)
190 .set E1,2 | which bit is E1 flag
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| D | util.S | 336 | else E1
435 | If E1, the format is from cmdreg1b{12:10}
446 clrl %d0 |if E1, size is always ext
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| D | res_func.S | 761 bclrb #E1,E_BYTE(%a6)
1221 bclrb #E1,E_BYTE(%a6)
1349 bclrb #E1,E_BYTE(%a6)
1455 bclrb #E1,E_BYTE(%a6)
1473 bclrb #E1,E_BYTE(%a6)
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| D | x_operr.S | 345 | Since operr is only an E1 exception, there is no need to frestore
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| D | x_snan.S | 115 bclrb #E1,E_BYTE(%a6)
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| /arch/arm/boot/dts/ |
| D | tango4-vantage-1172.dts | 7 model = "Sigma Designs SMP8758 Vantage-1172 Rev E1";
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| D | dove-sbc-a510.dts | 98 /* Ethernet0 depends on CM-A510 option E1 */
153 * PCIe0 can be configured by Jumper E1 to be either connected to
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| D | dove-cm-a510.dtsi | 56 * E1: PHY RTL8211D on internal GbE (SMI address 0x03)
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| /arch/c6x/kernel/ |
| D | switch_to.S | 58 B .S2 B3 ; return in next E1
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| /arch/arc/kernel/ |
| D | troubleshoot.c | 210 STS_BIT(regs, E2), STS_BIT(regs, E1)); in show_regs()
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| /arch/arm64/boot/dts/mediatek/ |
| D | mt8173-evb.dts | 296 /* Only MT8173 E1 needs USB power domain */
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