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Searched refs:IO_BASE (Results 1 – 25 of 25) sorted by relevance

/arch/mips/include/asm/txx9/
Drbtx4939.h19 #define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
20 #define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
21 #define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002)
22 #define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004)
23 #define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006)
24 #define RBTX4939_CONFIG3_ADDR (IO_BASE + TXX9_CE(1) + 0x00000008)
25 #define RBTX4939_CONFIG4_ADDR (IO_BASE + TXX9_CE(1) + 0x0000000a)
26 #define RBTX4939_USTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00001000)
27 #define RBTX4939_UDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001002)
28 #define RBTX4939_BDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001004)
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Drbtx4938.h19 #define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000)
20 #define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002)
21 #define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004)
22 #define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006)
23 #define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008)
24 #define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
25 #define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002)
26 #define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004)
27 #define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
28 #define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002)
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Drbtx4927.h37 #define RBTX4927_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
38 #define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
39 #define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
40 #define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
41 #define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
42 #define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
43 #define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
44 #define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000)
45 #define RBTX4927_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
/arch/arm/mach-rpc/include/mach/
Dhardware.h34 #define IO_BASE IOMEM(0xe0000000) macro
46 #define VIDC_BASE (IO_BASE + 0x00400000)
47 #define EXPMASK_BASE (IO_BASE + 0x00360000)
48 #define ECARD_IOC4_BASE (IO_BASE + 0x00270000)
49 #define ECARD_IOC_BASE (IO_BASE + 0x00240000)
50 #define IOMD_BASE (IO_BASE + 0x00200000)
51 #define IOC_BASE (IO_BASE + 0x00200000)
52 #define ECARD_MEMC8_BASE (IO_BASE + 0x0002b000)
53 #define FLOPPYDMA_BASE (IO_BASE + 0x0002a000)
54 #define PCIO_BASE (IO_BASE + 0x00010000)
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/arch/m68k/include/asm/
Dapollohw.h52 #define IO_BASE 0x80000000 macro
77 #define sio01 ((*(volatile struct SCN2681 *)(IO_BASE + sio01_physaddr)))
78 #define sio23 ((*(volatile struct SCN2681 *)(IO_BASE + sio23_physaddr)))
79 #define rtc (((volatile struct mc146818 *)(IO_BASE + rtc_physaddr)))
80 #define cpuctrl (*(volatile unsigned int *)(IO_BASE + cpuctrl_physaddr))
81 #define pica (IO_BASE + pica_physaddr)
82 #define picb (IO_BASE + picb_physaddr)
83 #define apollo_timer (IO_BASE + timer_physaddr)
84 #define addr_xlat_map ((unsigned short *)(IO_BASE + 0x17000))
86 …ne isaIO2mem(x) (((((x) & 0x3f8) << 7) | (((x) & 0xfc00) >> 6) | ((x) & 0x7)) + 0x40000 + IO_BASE)
/arch/mips/include/asm/mach-generic/
Dspaces.h34 #ifndef IO_BASE
35 #define IO_BASE _AC(0xa0000000, UL) macro
64 #ifndef IO_BASE
65 #define IO_BASE _AC(0x9000000000000000, UL) macro
/arch/mips/txx9/jmr3927/
Dsetup.c176 .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE, in jmr3927_rtc_init()
177 .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1, in jmr3927_rtc_init()
193 unsigned long iocled_base = JMR3927_IOC_LED_ADDR - IO_BASE; in jmr3927_device_init()
/arch/mips/include/asm/mach-ip22/
Dspaces.h19 #define IO_BASE 0xffffffffa0000000 macro
/arch/mips/include/asm/mach-cavium-octeon/
Dspaces.h17 #define IO_BASE _AC(0x8000000000000000, UL) macro
/arch/mips/include/asm/mach-ip27/
Dspaces.h20 #define IO_BASE 0x9200000000000000 macro
/arch/mips/txx9/rbtx4927/
Dsetup.c290 .start = RBTX4927_BRAMRTC_BASE - IO_BASE, in toshiba_rbtx4927_rtc_init()
291 .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1, in toshiba_rbtx4927_rtc_init()
353 txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL); in rbtx4927_device_init()
/arch/mips/include/asm/sibyte/
Dsb1250.h53 #define IOADDR(a) ((void __iomem *)(IO_BASE + (a)))
/arch/mips/txx9/generic/
Dpci.c196 set_io_port_base(IO_BASE + pcic->mem_resource[1].start); in txx9_alloc_pci_controller()
199 pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start; in txx9_alloc_pci_controller()
203 io_base - (mips_io_port_base - IO_BASE); in txx9_alloc_pci_controller()
204 pcic->io_offset = io_base - (mips_io_port_base - IO_BASE); in txx9_alloc_pci_controller()
/arch/arm/mach-integrator/
Dhardware.h14 #define IO_BASE 0xF0000000 // VA of IO macro
20 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
/arch/mips/sgi-ip27/
Dip27-init.c167 set_io_port_base(IO_BASE); in plat_mem_setup()
/arch/arm/mach-rpc/
Driscpc.c73 .virtual = (u32)IO_BASE,
Decard.c231 src_pgd = pgd_offset(mm, (unsigned long)IO_BASE); in ecard_init_pgtables()
/arch/mips/pci/
Dops-tx3927.c134 channel->io_resource->start + mips_io_port_base - IO_BASE; in tx3927_pcic_setup()
Dops-tx4927.c251 channel->io_map_base - IO_BASE) | in tx4927_pcic_setup()
/arch/mips/txx9/rbtx4939/
Dsetup.c46 ((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1))
448 unsigned long smc_addr = RBTX4939_ETHER_ADDR - IO_BASE; in rbtx4939_device_init()
/arch/arm/mach-lpc32xx/
Dlpc32xx.h706 #define IO_BASE 0xF0000000 macro
712 IO_BASE)
/arch/mips/txx9/rbtx4938/
Dsetup.c358 txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL); in rbtx4938_device_init()
/arch/mips/include/asm/sn/
Daddrs.h62 #define NODE_IO_BASE(_n) (IO_BASE + NODE_OFFSET(_n))
/arch/mips/include/asm/
Dio.h177 base = (u64) IO_BASE; in __ioremap_mode()
/arch/mips/kernel/
Dsetup.c676 if (UNCAC_BASE != IO_BASE) in resource_init()