| /arch/sh/kernel/cpu/sh3/ |
| D | setup-sh770x.c | 29 LCDC, PCC0, PCC1, enumerator
61 INTC_VECT(LCDC, 0x9a0),
82 { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
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| D | setup-sh7720.c | 226 DMAC1, LCDC, SSL, enumerator
246 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900),
270 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
|
| /arch/sh/kernel/cpu/sh4/ |
| D | setup-sh7760.c | 26 USB, LCDC, enumerator
55 INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
89 SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC,
110 { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
|
| /arch/sh/kernel/cpu/sh4a/ |
| D | setup-sh7366.c | 266 VEU2, LCDC, enumerator
301 INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
324 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
346 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
|
| D | setup-sh7343.c | 324 JPU, LCDC, enumerator
363 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
387 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
409 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
|
| D | setup-sh7763.c | 240 HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC, enumerator
258 INTC_VECT(LCDC, 0x620),
310 LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
326 { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
|
| D | setup-sh7734.c | 325 LCDC, enumerator
414 INTC_VECT(LCDC, 0xC40),
450 INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */
508 { SCIF0, SCIF3, HSCIF, LCDC } },
|
| D | setup-sh7722.c | 540 IRDA, JPU, LCDC, enumerator
576 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
601 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
623 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
|
| D | setup-sh7724.c | 888 LCDC, enumerator
992 INTC_VECT(LCDC, 0xF40),
1028 JPU, 0, 0, LCDC } },
1058 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
|
| /arch/sh/kernel/cpu/sh2a/ |
| D | setup-sh7203.c | 21 USB, LCDC, CMT0, CMT1, BSC, WDT, enumerator
60 INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
142 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
|