Home
last modified time | relevance | path

Searched refs:MFC_STATE1_MASTER_RUN_CONTROL_MASK (Results 1 – 6 of 6) sorted by relevance

/arch/powerpc/platforms/cell/spufs/
Dhw_ops.c231 sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_hw_master_start()
242 sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_hw_master_stop()
Dbacking_ops.c301 sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_start()
312 sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_stop()
Dswitch.c496 spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK | in setup_mfc_sr1()
1043 MFC_STATE1_MASTER_RUN_CONTROL_MASK); in clear_spu_status()
1055 MFC_STATE1_MASTER_RUN_CONTROL_MASK); in clear_spu_status()
1884 spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK); in force_spu_isolate_exit()
2150 MFC_STATE1_MASTER_RUN_CONTROL_MASK | in init_priv1()
/arch/powerpc/include/asm/
Dspu.h483 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull macro
/arch/powerpc/platforms/cell/
Dspu_base.c707 tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in crash_kexec_stop_spus()
/arch/powerpc/xmon/
Dxmon.c3927 tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in stop_spus()