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Searched refs:MIPS_CONF5_MSAEN (Results 1 – 6 of 6) sorted by relevance

/arch/mips/include/asm/
Dmsa.h100 set_c0_config5(MIPS_CONF5_MSAEN); in enable_msa()
108 clear_c0_config5(MIPS_CONF5_MSAEN); in disable_msa()
118 return read_c0_config5() & MIPS_CONF5_MSAEN; in is_msa_enabled()
Dmipsregs.h672 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) macro
/arch/mips/kvm/
Dmips.c1484 read_c0_config5() & MIPS_CONF5_MSAEN) in kvm_mips_handle_exit()
1575 set_c0_config5(MIPS_CONF5_MSAEN); in kvm_own_msa()
1635 set_c0_config5(MIPS_CONF5_MSAEN); in kvm_lose_fpu()
Dvz.c113 mask |= MIPS_CONF5_MSAEN; in kvm_vz_config5_guest_wrmask()
1525 !(read_gc0_config5() & MIPS_CONF5_MSAEN) || in kvm_trap_vz_handle_msa_disabled()
3058 MIPS_CONF5_MSAEN | in kvm_vz_vcpu_setup()
Demulate.c1248 mask |= MIPS_CONF5_MSAEN; in kvm_mips_config5_wrmask()
1487 if (change & MIPS_CONF5_MSAEN && in kvm_mips_emulate_CP0()
1489 change_c0_config5(MIPS_CONF5_MSAEN, in kvm_mips_emulate_CP0()
Dtrap_emul.c490 } else if (!(kvm_read_c0_guest_config5(cop0) & MIPS_CONF5_MSAEN)) { in kvm_trap_emul_handle_msa_disabled()