Searched refs:MSR_FE0 (Results 1 – 8 of 8) sorted by relevance
288 .fpexc_mode = MSR_FE0 | MSR_FE1, \334 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); in __unpack_fe01()339 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); in __pack_fe01()
103 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */ macro
376 regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1 | MSR_VEC | MSR_VSX); in restore_sigcontext()494 regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1 | MSR_VEC | MSR_VSX); in restore_tm_sigcontexts()
709 regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1); in restore_user_regs()797 regs->msr &= ~(MSR_FP | MSR_FE0 | MSR_FE1); in restore_tm_user_regs()
165 msr &= ~(MSR_FP|MSR_FE0|MSR_FE1); in __giveup_fpu()1865 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) in set_fpexc_mode()
1840 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)1841 xori r10,r10,(MSR_FE0|MSR_FE1)
1211 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
195 smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE | in kvmppc_recalc_shadow_msr()198 smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE; in kvmppc_recalc_shadow_msr()571 to_book3s(vcpu)->msr_mask &= ~(MSR_FE0 | MSR_FE1); in kvmppc_set_pvr_pr()