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Searched refs:MSR_IR (Results 1 – 25 of 33) sorted by relevance

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/arch/powerpc/kvm/
Dbook3s_32_mmu.c361 if (msr & (MSR_DR|MSR_IR)) { in kvmppc_mmu_book3s_32_esid_to_vsid()
370 switch (msr & (MSR_DR|MSR_IR)) { in kvmppc_mmu_book3s_32_esid_to_vsid()
374 case MSR_IR: in kvmppc_mmu_book3s_32_esid_to_vsid()
380 case MSR_DR|MSR_IR: in kvmppc_mmu_book3s_32_esid_to_vsid()
Dbook3s_64_mmu.c498 if (kvmppc_get_msr(vcpu) & MSR_IR) { in kvmppc_mmu_book3s_64_slbia()
597 if (msr & (MSR_DR|MSR_IR)) { in kvmppc_mmu_book3s_64_esid_to_vsid()
610 switch (msr & (MSR_DR|MSR_IR)) { in kvmppc_mmu_book3s_64_esid_to_vsid()
614 case MSR_IR: in kvmppc_mmu_book3s_64_esid_to_vsid()
620 case MSR_DR|MSR_IR: in kvmppc_mmu_book3s_64_esid_to_vsid()
Dbook3s_rmhandlers.S151 li r6, MSR_IR | MSR_DR
Dbook3s_pr.c69 return (msr & (MSR_IR|MSR_DR)) == MSR_DR; in kvmppc_is_split_real()
78 if ((msr & (MSR_IR|MSR_DR)) != MSR_DR) in kvmppc_fixup_split_real()
201 smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE; in kvmppc_recalc_shadow_msr()
495 if ((kvmppc_get_msr(vcpu) & (MSR_PR|MSR_IR|MSR_DR)) != in kvmppc_set_msr_pr()
496 (old_msr & (MSR_PR|MSR_IR|MSR_DR))) { in kvmppc_set_msr_pr()
677 bool ir = (kvmppc_get_msr(vcpu) & MSR_IR) ? true : false; in kvmppc_handle_pagefault()
698 switch (kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) { in kvmppc_handle_pagefault()
708 case MSR_IR: in kvmppc_handle_pagefault()
711 if ((kvmppc_get_msr(vcpu) & (MSR_DR|MSR_IR)) == MSR_DR) in kvmppc_handle_pagefault()
Dbook3s.c457 int relocated = (kvmppc_get_msr(vcpu) & (data ? MSR_DR : MSR_IR)); in kvmppc_xlate()
471 if ((kvmppc_get_msr(vcpu) & (MSR_IR | MSR_DR)) == MSR_DR && in kvmppc_xlate()
Dbook3s_hv_builtin.c211 if (kvm_is_radix(vcpu->kvm) && (mfmsr() & MSR_IR)) in kvmppc_h_random()
/arch/powerpc/platforms/powernv/
Dopal-wrappers.S27 li r0,MSR_IR|MSR_DR|MSR_LE
Dsubcore-asm.S31 li r5, MSR_IR|MSR_DR
Didle.c389 WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); in power7_idle_insn()
700 WARN_ON_ONCE(mfmsr() & (MSR_IR|MSR_DR)); in power9_idle_stop()
Dopal-call.c100 bool mmu = (msr & (MSR_IR|MSR_DR)); in opal_call()
/arch/powerpc/platforms/82xx/
Dpq2.c27 mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR)); in pq2_restart()
/arch/powerpc/platforms/pasemi/
Dpowersave.S62 LOAD_REG_IMMEDIATE(r6,MSR_DR|MSR_IR|MSR_ME|MSR_EE)
/arch/powerpc/kernel/
Dhead_32.h52 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR) /* can take exceptions */
82 LOAD_REG_IMMEDIATE(r10, MSR_KERNEL & ~(MSR_IR|MSR_DR)) /* can take exceptions */
Dhead_32.S217 ori r0,r0,MSR_DR|MSR_IR|MSR_RI
919 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1057 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR)
1079 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI)
1097 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
Dpaca.c192 new_paca->kernel_msr = MSR_KERNEL & ~(MSR_IR | MSR_DR); in initialise_paca()
Dhead_40x.S615 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */
783 lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h
784 ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l
Dkvm_emul.S300 andi. r31, r31, MSR_DR | MSR_IR
Dhead_8xx.S100 ori r0,r0,MSR_DR|MSR_IR
757 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
Dmisc_64.S492 li r10,MSR_DR|MSR_IR
Dhead_64.S465 andi. r0,r3,MSR_IR|MSR_DR
/arch/powerpc/xmon/
Dxmon.c514 if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT)) in xmon_core()
659 if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT)) { in xmon_core()
709 if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) != (MSR_IR|MSR_64BIT)) in xmon_bpt()
740 if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) != (MSR_IR|MSR_64BIT)) in xmon_break_match()
750 if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) != (MSR_IR|MSR_64BIT)) in xmon_iabr_match()
775 if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT)) { in xmon_fault_handler()
1126 if ((regs->msr & (MSR_64BIT|MSR_PR|MSR_IR)) == (MSR_64BIT|MSR_IR)) { in do_step()
/arch/powerpc/include/asm/
Dreg.h109 #define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */ macro
138 #define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV)
151 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
Dreg_booke.h46 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
/arch/powerpc/platforms/52xx/
Dlite5200_sleep.S207 ori r10, r10, MSR_DR | MSR_IR
/arch/powerpc/platforms/pseries/
Dras.c476 (MSR_LE|MSR_RI|MSR_DR|MSR_IR|MSR_ME|MSR_PR| in pSeries_system_reset_exception()

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