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Searched refs:R1 (Results 1 – 25 of 41) sorted by relevance

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/arch/x86/crypto/
Dtwofish-x86_64-asm_64.S34 #define R1 %rbx macro
206 pushq R1
215 movq (R3), R1
217 input_whitening(R1,%r11,a_offset)
221 shr $32, R1
226 encrypt_round(R0,R1,R2,R3,0);
227 encrypt_round(R2,R3,R0,R1,8);
228 encrypt_round(R0,R1,R2,R3,2*8);
229 encrypt_round(R2,R3,R0,R1,3*8);
230 encrypt_round(R0,R1,R2,R3,4*8);
[all …]
Dtwofish-i586-asm_32.S231 encrypt_round(R0,R1,R2,R3,0);
232 encrypt_round(R2,R3,R0,R1,8);
233 encrypt_round(R0,R1,R2,R3,2*8);
234 encrypt_round(R2,R3,R0,R1,3*8);
235 encrypt_round(R0,R1,R2,R3,4*8);
236 encrypt_round(R2,R3,R0,R1,5*8);
237 encrypt_round(R0,R1,R2,R3,6*8);
238 encrypt_round(R2,R3,R0,R1,7*8);
239 encrypt_round(R0,R1,R2,R3,8*8);
240 encrypt_round(R2,R3,R0,R1,9*8);
[all …]
/arch/hexagon/kernel/
Dvm_entry.S207 memd(R29 + #(_PT_R0100 + -_PT_REGS_SIZE)) = R1:0; \
214 memd(R29 + #_PT_ER_VMEL) = R1:0; \
216 R1.L = #LO(CHandler); \
220 R1.H = #HI(CHandler); \
230 memd(R29 + #(_PT_R0100 + -_PT_REGS_SIZE)) = R1:0; \
239 R1:0 = G1:0; \
241 memd(R29 + #_PT_ER_VMEL) = R1:0; \
242 R1 = # ## #(CHandler); \
302 R1 = memw(THREADINFO_REG + #_THREAD_INFO_FLAGS); define
321 R1:0 = memd(R29 + #_PT_ER_VMEL);
[all …]
Dvm_switch.S58 R29 = memw(R1 + #(_TASK_STRUCT_THREAD + _THREAD_STRUCT_SWITCH_SP));
75 THREADINFO_REG = memw(R1 + #_TASK_THREAD_INFO);
Dhead.S95 R1.H = #HI(PAGE_OFFSET >> (22 - 2))
96 R1.L = #LO(PAGE_OFFSET >> (22 - 2))
153 memw(R1 ++ #4) = R0
/arch/sparc/net/
Dbpf_jit_comp_32.c261 #define emit_cmp(R1, R2) \ argument
262 *prog++ = (SUBCC | RS1(R1) | RS2(R2) | RD(G0))
264 #define emit_cmpi(R1, IMM) \ argument
265 *prog++ = (SUBCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
267 #define emit_btst(R1, R2) \ argument
268 *prog++ = (ANDCC | RS1(R1) | RS2(R2) | RD(G0))
270 #define emit_btsti(R1, IMM) \ argument
271 *prog++ = (ANDCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
273 #define emit_sub(R1, R2, R3) \ argument
274 *prog++ = (SUB | RS1(R1) | RS2(R2) | RD(R3))
[all …]
Dbpf_jit_comp_64.c646 #define emit_cmp(R1, R2, CTX) \ argument
647 emit(SUBCC | RS1(R1) | RS2(R2) | RD(G0), CTX)
649 #define emit_cmpi(R1, IMM, CTX) \ argument
650 emit(SUBCC | IMMED | RS1(R1) | S13(IMM) | RD(G0), CTX)
652 #define emit_btst(R1, R2, CTX) \ argument
653 emit(ANDCC | RS1(R1) | RS2(R2) | RD(G0), CTX)
655 #define emit_btsti(R1, IMM, CTX) \ argument
656 emit(ANDCC | IMMED | RS1(R1) | S13(IMM) | RD(G0), CTX)
/arch/arm/boot/dts/
Dimx6qdl-gw552x.dtsi147 /* VDD_SOC (1+R1/R2 = 1.635) */
158 /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */
169 /* VDD_ARM (1+R1/R2 = 1.635) */
180 /* VDD_DDR (1+R1/R2 = 2.105) */
191 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
201 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dimx6qdl-gw51xx.dtsi157 /* VDD_SOC (1+R1/R2 = 1.635) */
168 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
179 /* VDD_ARM (1+R1/R2 = 1.635) */
190 /* VDD_DDR (1+R1/R2 = 2.105) */
201 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
211 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dimx6qdl-gw53xx.dtsi211 /* VDD_SOC (1+R1/R2 = 1.635) */
222 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
233 /* VDD_ARM (1+R1/R2 = 1.635) */
244 /* VDD_DDR (1+R1/R2 = 2.105) */
255 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
273 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dimx6qdl-gw553x.dtsi185 /* VDD_SOC (1+R1/R2 = 1.635) */
196 /* VDD_DDR (1+R1/R2 = 2.105) */
207 /* VDD_ARM (1+R1/R2 = 1.635) */
218 /* VDD_3P3 (1+R1/R2 = 1.281) */
229 /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */
247 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dimx6qdl-gw52xx.dtsi220 /* VDD_SOC (1+R1/R2 = 1.635) */
231 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
242 /* VDD_ARM (1+R1/R2 = 1.635) */
253 /* VDD_DDR (1+R1/R2 = 2.105) */
264 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
282 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dimx6qdl-gw551x.dtsi225 /* VDD_SOC (1+R1/R2 = 1.635) */
236 /* VDD_DDR (1+R1/R2 = 2.105) */
247 /* VDD_ARM (1+R1/R2 = 1.635) */
258 /* VDD_3P3 (1+R1/R2 = 1.281) */
269 /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */
287 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dimx6qdl-gw5904.dtsi258 /* VDD_SOC (1+R1/R2 = 1.635) */
269 /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
280 /* VDD_ARM (1+R1/R2 = 1.635) */
291 /* VDD_DDR (1+R1/R2 = 2.105) */
302 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
312 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dimx6qdl-gw5903.dtsi236 /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */
247 /* VDD_DDR (1+R1/R2 = 2.105) */
258 /* VDD_ARM (1+R1/R2 = 1.635) */
270 /* VDD_SOC (1+R1/R2 = 1.635) */
282 /* VDD_1P0 (1+R1/R2 = 1.38): */
292 /* VDD_HIGH (1+R1/R2 = 4.17) */
Dsun8i-h2-plus-orangepi-r1.dts43 /* Orange Pi R1 is based on Orange Pi Zero design */
47 model = "Xunlong Orange Pi R1";
Dimx6qdl-gw560x.dtsi329 /* VDD_DDR (1+R1/R2 = 2.105) */
340 /* VDD_ARM (1+R1/R2 = 1.931) */
352 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
363 /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */
381 /* VDD_HIGH (1+R1/R2 = 4.17) */
Drv1108-elgin-r1.dts12 model = "Elgin RV1108 R1 board";
/arch/powerpc/lib/
Dldstfp.S168 STXVD2X(0,R1,R8)
175 LXVD2X(0,R1,R8)
193 STXVD2X(0,R1,R8)
199 LXVD2X(0,R1,R8)
/arch/s390/crypto/
Dcrc32le-vx.S64 .quad 0x1c6e41596, 0x154442bd4 # R2, R1
72 .quad 0x09e4addf8, 0x740eef02 # R2, R1
Dcrc32be-vx.S62 .quad 0x08833794c, 0x0e6228b11 # R1, R2
/arch/parisc/kernel/
Dunaligned.c107 #define R1(i) (((i)>>21)&0x1f) macro
438 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0; in handle_unaligned()
654 if (ret == 0 && modify && R1(regs->iir)) in handle_unaligned()
655 regs->gr[R1(regs->iir)] = newbase; in handle_unaligned()
/arch/mips/include/asm/
Dmipsregs.h1255 #define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \ argument
1256 __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t" \
1257 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1262 #define _ASM_MACRO_2R(OP, R1, R2, ENC) \ argument
1263 __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \
1264 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1270 #define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \ argument
1271 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \
1272 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1279 #define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \ argument
[all …]
/arch/mips/bcm47xx/
DKconfig20 This will generate an image with support for SSB and MIPS32 R1 instruction set.
/arch/nios2/platform/
DKconfig.platform59 Select between Nios II R1 and Nios II R2 . The architectures
60 are binary incompatible. Default is R1 .

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