Searched refs:REG_OFFSET (Results 1 – 17 of 17) sorted by relevance
| /arch/arm64/kvm/ |
| D | regmap.c | 17 #define REG_OFFSET(_reg) \ macro
20 #define USR_REG_OFFSET(R) REG_OFFSET(compat_usr(R))
30 REG_OFFSET(pc)
38 REG_OFFSET(compat_r8_fiq), /* r8 */
39 REG_OFFSET(compat_r9_fiq), /* r9 */
40 REG_OFFSET(compat_r10_fiq), /* r10 */
41 REG_OFFSET(compat_r11_fiq), /* r11 */
42 REG_OFFSET(compat_r12_fiq), /* r12 */
43 REG_OFFSET(compat_sp_fiq), /* r13 */
44 REG_OFFSET(compat_lr_fiq), /* r14 */
[all …]
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| /arch/arm/kvm/ |
| D | emulate.c | 23 #define REG_OFFSET(_reg) \ macro
26 #define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])
43 REG_OFFSET(fiq_regs[0]), /* r8 */
44 REG_OFFSET(fiq_regs[1]), /* r9 */
45 REG_OFFSET(fiq_regs[2]), /* r10 */
46 REG_OFFSET(fiq_regs[3]), /* r11 */
47 REG_OFFSET(fiq_regs[4]), /* r12 */
48 REG_OFFSET(fiq_regs[5]), /* r13 */
49 REG_OFFSET(fiq_regs[6]), /* r14 */
59 REG_OFFSET(irq_regs[0]), /* r13 */
[all …]
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| /arch/mips/ar7/ |
| D | irq.c | 19 #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10) macro
22 #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
24 #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
26 #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
30 #define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
31 #define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
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| /arch/arm/mach-ixp4xx/ |
| D | gtwx5715-setup.c | 71 #define REG_OFFSET 3 macro
73 #define REG_OFFSET 0 macro
98 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | coyote-setup.c | 67 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
104 (char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET); in coyote_init()
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| D | avila-setup.c | 89 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
98 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | dsmg600-setup.c | 137 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
146 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | omixp-setup.c | 127 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
135 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
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| D | vulcan-setup.c | 84 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
93 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | nslu2-setup.c | 160 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
169 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | fsg-setup.c | 100 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
109 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | nas100d-setup.c | 140 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
149 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | gateway7001-setup.c | 61 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | wg302v2-setup.c | 62 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | ixdp425-setup.c | 162 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
171 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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| D | goramo_mlr.c | 245 REG_OFFSET,
255 REG_OFFSET,
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| /arch/arm/mach-ixp4xx/include/mach/ |
| D | platform.h | 22 #define REG_OFFSET 0 macro
24 #define REG_OFFSET 3 macro
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