/arch/mips/mm/ |
D | uasm-mips.c | 51 [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, 52 [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD}, 53 [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD}, 54 [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, 55 [insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 56 [insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 57 [insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 58 [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 59 [insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM}, 60 [insn_bgezl] = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM}, [all …]
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D | uasm-micromips.c | 43 [insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD}, 44 [insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM}, 45 [insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD}, 46 [insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM}, 47 [insn_beq] = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, 49 [insn_bgez] = {M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM}, 51 [insn_bltz] = {M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM}, 53 [insn_bne] = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM}, 54 [insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM}, 55 [insn_cfc1] = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS}, [all …]
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D | uasm.c | 17 RS = 0x001, enumerator
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/arch/powerpc/xmon/ |
D | ppc-opc.c | 565 #define RS RC + 1 macro 566 #define RT RS 568 #define RD RS 573 #define RSQ RS + 1 3260 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3263 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, 3265 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 3266 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, 3268 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, 3269 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, [all …]
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/arch/powerpc/platforms/powermac/ |
D | time.c | 53 #define RS 0x200 /* skip between registers */ macro 54 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */ 55 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */ 56 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */ 57 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */ 58 #define ACR (11*RS) /* Auxiliary control register */ 59 #define IFR (13*RS) /* Interrupt flag register */
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/arch/arm/boot/dts/ |
D | kirkwood-openrd.dtsi | 60 * SelRS232or485 selects between RS-232 or RS-485 63 * Low: RS-232 64 * High: RS-485
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D | aspeed-bmc-opp-romulus.dts | 138 /* Rear RS-232 connector */
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D | vf610-zii-scu4-aib.dts | 842 VF610_PAD_PTB25__UART1_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ 850 VF610_PAD_PTD2__UART2_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */
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D | aspeed-bmc-opp-palmetto.dts | 115 /* Rear RS-232 connector */
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D | aspeed-bmc-lenovo-hr630.dts | 103 /* Rear RS-232 connector */
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D | aspeed-bmc-opp-witherspoon.dts | 262 /* Rear RS-232 connector */
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D | aspeed-bmc-lenovo-hr855xg2.dts | 113 /* Rear RS-232 connector */
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D | aspeed-bmc-inspur-fp5280g2.dts | 201 /* Rear RS-232 connector */
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D | aspeed-bmc-opp-mihawk.dts | 421 /* Rear RS-232 connector */
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D | aspeed-bmc-opp-swift.dts | 290 /* Rear RS-232 connector */
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/arch/powerpc/include/asm/ |
D | asm-compat.h | 23 #define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS) argument
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D | ppc_asm.h | 422 #define MTOCRF(FXM, RS) \ 424 mtcrf (FXM), RS; \ 426 mtocrf (FXM), RS; \
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/arch/m68k/fpsp040/ |
D | stan.S | 236 fmulx %fp0,%fp2 | ...RS(P1+S(P2+SP3)) 241 faddx %fp2,%fp0 | ...R+RS(P1+S(P2+SP3)) 274 fmulx %fp1,%fp2 | ...RS(P1+S(P2+SP3)) 279 faddx %fp2,%fp1 | ...R+RS(P1+S(P2+SP3))
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/arch/powerpc/ |
D | Kconfig | 953 have an IBM RS/6000 or pSeries machine, say Y. If you have an
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/arch/m68k/ifpsp060/src/ |
D | fplsp.S | 5822 fmul.x %fp0,%fp2 # RS(P1+S(P2+SP3)) 5826 fadd.x %fp2,%fp0 # R+RS(P1+S(P2+SP3)) 5859 fmul.x %fp1,%fp2 # RS(P1+S(P2+SP3)) 5863 fadd.x %fp2,%fp1 # R+RS(P1+S(P2+SP3))
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