| /arch/powerpc/kernel/ |
| D | cpu_setup_ppc970.S | 76 mfspr r0,SPRN_HID0
90 mfspr r0,SPRN_HID0
97 mtspr SPRN_HID0,r0
98 mfspr r0,SPRN_HID0
99 mfspr r0,SPRN_HID0
100 mfspr r0,SPRN_HID0
101 mfspr r0,SPRN_HID0
102 mfspr r0,SPRN_HID0
103 mfspr r0,SPRN_HID0
119 mfspr r3,SPRN_HID0
[all …]
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| D | l2cr_6xx.S | 116 mfspr r8,SPRN_HID0 /* Save HID0 in r8 */
119 mtspr SPRN_HID0,r4 /* Disable DPM */
433 mfspr r3,SPRN_HID0
435 mtspr SPRN_HID0,r3
448 mfspr r3,SPRN_HID0
452 mtspr SPRN_HID0,r3
454 mtspr SPRN_HID0,r3
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| D | cpu_setup_6xx.S | 85 mfspr r11,SPRN_HID0
92 mtspr SPRN_HID0,r8 /* enable and invalidate caches */
94 mtspr SPRN_HID0,r11 /* enable caches */
103 mfspr r11,SPRN_HID0
107 mtspr SPRN_HID0,r8 /* flush branch target address cache */
109 mtspr SPRN_HID0,r11
162 mfspr r11,SPRN_HID0
176 mtspr SPRN_HID0,r11
232 mfspr r11,SPRN_HID0
257 mtspr SPRN_HID0,r11
[all …]
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| D | idle_6xx.S | 31 mfspr r4,SPRN_HID0
33 mtspr SPRN_HID0, r4
120 mfspr r4,SPRN_HID0
130 mtspr SPRN_HID0,r4
166 mfspr r9,SPRN_HID0
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| D | pmc.c | 82 hid0 = mfspr(SPRN_HID0); in power4_enable_pmcs()
95 "isync" : "=&r" (hid0) : "i" (SPRN_HID0), "0" (hid0): in power4_enable_pmcs()
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| D | idle_e500.S | 59 mfspr r4,SPRN_HID0
63 mtspr SPRN_HID0,r4
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| D | cpu_setup_fsl_booke.S | 114 mfspr r3,SPRN_HID0
116 mtspr SPRN_HID0,r3
257 mfspr r8,SPRN_HID0
259 mtspr SPRN_HID0,r9
279 mtspr SPRN_HID0,r8
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| D | misc_32.S | 164 mfspr r5,SPRN_HID0
167 mtspr SPRN_HID0,r5
192 mfspr r5,SPRN_HID0
195 mtspr SPRN_HID0,r5
310 mfspr r3,SPRN_HID0
312 mtspr SPRN_HID0,r3
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| D | head_32.S | 1215 mfspr r11, SPRN_HID0
1219 mtspr SPRN_HID0, r11
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| /arch/powerpc/sysdev/ |
| D | 6xx-suspend.S | 19 mfspr r5, SPRN_HID0
22 mtspr SPRN_HID0, r5
43 mfspr r5, SPRN_HID0
45 mtspr SPRN_HID0, r5
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| /arch/powerpc/platforms/powermac/ |
| D | cache.S | 56 mfspr r8,SPRN_HID0 /* Save SPRN_HID0 in r8 */
59 mtspr SPRN_HID0,r4 /* Disable DPM */
85 mfspr r3,SPRN_HID0
87 mtspr SPRN_HID0,r3
93 mtspr SPRN_HID0,r3
95 mtspr SPRN_HID0,r3
167 mfspr r0,SPRN_HID0
169 mtspr SPRN_HID0,r0
175 mfspr r0,SPRN_HID0
177 mtspr SPRN_HID0,r0
[all …]
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| D | sleep.S | 227 mfspr r2,SPRN_HID0
232 mtspr SPRN_HID0,r2
261 mfspr r3,SPRN_HID0
264 mtspr SPRN_HID0,r3
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| /arch/powerpc/platforms/powernv/ |
| D | subcore.c | 168 opal_slw_set_reg(cpu_pir, SPRN_HID0, hid0); in update_hid_in_slw()
181 while (mfspr(SPRN_HID0) & mask) in unsplit_core()
188 hid0 = mfspr(SPRN_HID0); in unsplit_core()
193 while (mfspr(SPRN_HID0) & mask) in unsplit_core()
225 hid0 = mfspr(SPRN_HID0); in split_core()
231 while (!(mfspr(SPRN_HID0) & split_parms[i].mask)) in split_core()
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| D | subcore-asm.S | 60 1: mfspr r4, SPRN_HID0
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| D | idle.c | 75 uint64_t hid0_val = mfspr(SPRN_HID0); in pnv_save_sprs_for_deep_states()
114 rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); in pnv_save_sprs_for_deep_states()
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| /arch/powerpc/platforms/86xx/ |
| D | common.c | 34 temp = mfspr(SPRN_HID0); in mpc86xx_time_init()
36 mtspr(SPRN_HID0, temp); in mpc86xx_time_init()
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| /arch/powerpc/platforms/52xx/ |
| D | mpc52xx_sleep.S | 38 mfspr r10, SPRN_HID0
41 mtspr SPRN_HID0, r10
54 mfspr r10, SPRN_HID0
58 mtspr SPRN_HID0, r10
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| D | lite5200_sleep.S | 94 mfspr r3, SPRN_HID0
98 mtspr SPRN_HID0, r3
227 mfspr r10, SPRN_HID0
229 mtspr SPRN_HID0, r5 /* invalidate caches */
231 mtspr SPRN_HID0, r10
236 mtspr SPRN_HID0, r10 /* restore (enable caches, DPM) */
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| D | mpc52xx_pm.c | 151 hid0 = mfspr(SPRN_HID0); in mpc52xx_pm_enter()
152 mtspr(SPRN_HID0, (hid0 & ~(HID0_DOZE | HID0_NAP | HID0_DPM)) | HID0_SLEEP); in mpc52xx_pm_enter()
168 mtspr(SPRN_HID0, hid0); in mpc52xx_pm_enter()
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| /arch/powerpc/platforms/85xx/ |
| D | mpc85xx_pm_ops.c | 34 tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP; in mpc85xx_cpu_die()
35 mtspr(SPRN_HID0, tmp); in mpc85xx_cpu_die()
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| /arch/powerpc/platforms/83xx/ |
| D | suspend-asm.S | 69 mfspr r5, SPRN_HID0
277 mfspr r3, SPRN_HID0
279 mtspr SPRN_HID0, r3
344 mfspr r5, SPRN_HID0
347 mtspr SPRN_HID0, r5
397 mtspr SPRN_HID0, r5
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| /arch/powerpc/platforms/cell/ |
| D | ras.c | 334 hid0 = mfspr(SPRN_HID0); in cbe_ras_init()
337 mtspr(SPRN_HID0, hid0); in cbe_ras_init()
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| /arch/powerpc/kvm/ |
| D | e500_emulate.c | 257 case SPRN_HID0: in kvmppc_core_emulate_mtspr_e500()
385 case SPRN_HID0: in kvmppc_core_emulate_mfspr_e500()
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| D | book3s_emulate.c | 715 case SPRN_HID0: in kvmppc_core_emulate_mtspr_pr()
898 case SPRN_HID0: in kvmppc_core_emulate_mfspr_pr()
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| /arch/powerpc/include/asm/ |
| D | reg.h | 543 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ macro
1459 asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0)); in update_power8_hid0()
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