| /arch/mips/kernel/ |
| D | unaligned.c | 95 #define STR(x) __STR(x) macro
127 STR(PTR)"\t1b, 4b\n\t" \
128 STR(PTR)"\t2b, 4b\n\t" \
148 STR(PTR)"\t1b, 4b\n\t" \
149 STR(PTR)"\t2b, 4b\n\t" \
181 STR(PTR)"\t1b, 11b\n\t" \
182 STR(PTR)"\t2b, 11b\n\t" \
183 STR(PTR)"\t3b, 11b\n\t" \
184 STR(PTR)"\t4b, 11b\n\t" \
209 STR(PTR)"\t1b, 4b\n\t" \
[all …]
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| D | mips-r2-to-r6-emul.c | 1261 STR(PTR) " 1b,8b\n" in mipsr2_decoder()
1262 STR(PTR) " 2b,8b\n" in mipsr2_decoder()
1263 STR(PTR) " 3b,8b\n" in mipsr2_decoder()
1264 STR(PTR) " 4b,8b\n" in mipsr2_decoder()
1336 STR(PTR) " 1b,8b\n" in mipsr2_decoder()
1337 STR(PTR) " 2b,8b\n" in mipsr2_decoder()
1338 STR(PTR) " 3b,8b\n" in mipsr2_decoder()
1339 STR(PTR) " 4b,8b\n" in mipsr2_decoder()
1407 STR(PTR) " 1b,8b\n" in mipsr2_decoder()
1408 STR(PTR) " 2b,8b\n" in mipsr2_decoder()
[all …]
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| D | syscall.c | 124 " "STR(PTR)" 1b, 4b \n" in mips_atomic_set()
125 " "STR(PTR)" 2b, 4b \n" in mips_atomic_set()
154 " "STR(PTR)" 1b, 5b \n" in mips_atomic_set()
155 " "STR(PTR)" 2b, 5b \n" in mips_atomic_set()
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| /arch/mips/cavium-octeon/crypto/ |
| D | octeon-crypto.h | 34 "dmtc2 %[rt],0x0048+" STR(index) \
47 "dmfc2 %[rt],0x0048+" STR(index) \
60 "dmtc2 %[rt],0x0040+" STR(index) \
108 "dmtc2 %[rt],0x0250+" STR(index) \
121 "dmfc2 %[rt],0x0250+" STR(index) \
134 "dmtc2 %[rt],0x0240+" STR(index) \
182 "dmtc2 %[rt],0x0250+" STR(index) \
195 "dmfc2 %[rt],0x0250+" STR(index) \
208 "dmtc2 %[rt],0x0240+" STR(index) \
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| /arch/mips/include/asm/ |
| D | ftrace.h | 35 STR(PTR) "\t1b, 3b\n\t" \
57 STR(PTR) "\t1b, 3b\n\t" \
67 safe_load(STR(lw), src, dst, error)
69 safe_store(STR(sw), src, dst, error)
72 safe_load(STR(PTR_L), src, dst, error)
75 safe_store(STR(PTR_S), src, dst, error)
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| D | r4kcache.h | 115 " "STR(PTR)" 1b, 3b \n" \
139 " "STR(PTR)" 1b, 3b \n" \
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| D | mipsregs.h | 29 #ifndef STR
30 #define STR(x) __STR(x) macro
2284 " "STR(gas_hardfloat)" \n" \
2285 " cfc1 %0,"STR(source)" \n" \
2296 " "STR(gas_hardfloat)" \n" \
2297 " ctc1 %0,"STR(dest)" \n" \
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| /arch/m68k/lib/ |
| D | checksum.c | 290 #define STR(X) STR1(X) in csum_partial_copy_from_user() macro
292 "moveq #-" STR(EFAULT) ",%5\n\t" in csum_partial_copy_from_user()
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| /arch/x86/kernel/ |
| D | machine_kexec_32.c | 41 #define STR(X) __STR(X) in load_segments() macro
44 "\tljmp $"STR(__KERNEL_CS)",$1f\n" in load_segments()
46 "\tmovl $"STR(__KERNEL_DS)",%%eax\n" in load_segments()
51 #undef STR in load_segments()
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| /arch/mips/include/asm/vdso/ |
| D | vdso.h | 51 " " STR(PTR_ADDU) " %0, $31, %0 \n" in get_vdso_base()
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| /arch/nds32/kernel/ |
| D | ftrace.c | 52 #define XSTR(s) STR(s)
53 #define STR(s) #s macro
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| /arch/m68k/include/asm/ |
| D | entry.h | 244 #define STR(X) STR1(X) macro
255 "andw #-"STR(THREAD_SIZE)","#tmp"\n\t" \
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| /arch/parisc/include/asm/ |
| D | unistd.h | 179 #undef STR
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| /arch/arm/boot/dts/ |
| D | vf610-zii-dev.dtsi | 186 * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR
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| /arch/powerpc/kernel/ |
| D | ptrace.c | 66 #define STR(s) #s /* convert to string */ macro
69 {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \
70 {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
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| /arch/arm/mm/ |
| D | Kconfig | 918 DMA cache maintenance functions is performed. These LDR/STR
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| /arch/x86/lib/ |
| D | x86-opcode-map.txt | 940 1: STR Rv/Mw
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| /arch/arm/ |
| D | Kconfig | 1053 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
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| /arch/x86/ |
| D | Kconfig | 1893 or STR instructions are executed in user mode. These instructions
|