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Searched refs:TIMER1_2_CONTROL_OFFSET (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-cns3xxx/
Dcore.c115 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_shutdown()
121 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_set_oneshot()
125 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_set_oneshot()
131 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_set_periodic()
138 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_set_periodic()
145 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_timer_set_next_event()
148 writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_timer_set_next_event()
211 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in __cns3xxx_timer_init()
229 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in __cns3xxx_timer_init()
231 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in __cns3xxx_timer_init()
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Dcns3xxx.h127 #define TIMER1_2_CONTROL_OFFSET 0x30 macro