| /arch/mips/include/asm/mach-pic32/ |
| D | pic32.h | 14 #define PIC32_CLR(_reg) ((_reg) + 0x04) argument
15 #define PIC32_SET(_reg) ((_reg) + 0x08) argument
16 #define PIC32_INV(_reg) ((_reg) + 0x0C) argument
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| /arch/arm/mach-mmp/ |
| D | clock.h | 25 #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ argument
27 .clk_rst = APBC_##_reg, \
33 #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \ argument
35 .clk_rst = APBC_##_reg, \
41 #define APMU_CLK(_name, _reg, _eval, _rate) \ argument
43 .clk_rst = APMU_##_reg, \
49 #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \ argument
51 .clk_rst = APMU_##_reg, \
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| /arch/mips/include/asm/ |
| D | kvm_host.h | 471 #define __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \ argument
474 return cop0->reg[(_reg)][(sel)]; \
479 cop0->reg[(_reg)][(sel)] = val; \
483 #define __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \ argument
487 cop0->reg[(_reg)][(sel)] |= val; \
492 cop0->reg[(_reg)][(sel)] &= ~val; \
499 cop0->reg[(_reg)][(sel)] &= ~_mask; \
500 cop0->reg[(_reg)][(sel)] |= val & _mask; \
504 #define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \ argument
508 _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
[all …]
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| /arch/arm/kvm/ |
| D | emulate.c | 23 #define REG_OFFSET(_reg) \ argument
24 (offsetof(struct kvm_regs, _reg) / sizeof(u32))
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| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7366.c | 108 #define DIV4(_reg, _bit, _mask, _flags) \ argument
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
128 #define MSTP(_parent, _reg, _bit, _flags) \ argument
129 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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| D | clock-sh7343.c | 105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
125 #define MSTP(_parent, _reg, _bit, _flags) \ argument
126 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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| D | clock-sh7722.c | 108 #define DIV4(_reg, _bit, _mask, _flags) \ argument
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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| D | clock-sh7734.c | 69 #define DIV4(_reg, _bit, _mask, _flags) \ argument
70 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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| D | clock-sh7723.c | 111 #define DIV4(_reg, _bit, _mask, _flags) \ argument
112 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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| D | clock-sh7724.c | 150 #define DIV4(_reg, _bit, _mask, _flags) \ argument
151 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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| /arch/sh/kernel/cpu/sh2a/ |
| D | clock-sh7264.c | 77 #define DIV4(_reg, _bit, _mask, _flags) \ argument
78 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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| D | clock-sh7269.c | 105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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| /arch/arm64/kvm/ |
| D | regmap.c | 17 #define REG_OFFSET(_reg) \ argument
18 (offsetof(struct user_pt_regs, _reg) / sizeof(unsigned long))
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| /arch/ia64/kernel/ |
| D | head.S | 65 #define SAVE_ONE_RR(num, _reg, _tmp) \ argument
67 mov _reg=rr[_tmp]
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| /arch/x86/kvm/vmx/ |
| D | vmx.c | 6976 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ in nested_vmx_cr_fixed1_bits_update() argument
6977 if (entry && (entry->_reg & (_cpuid_mask))) \ in nested_vmx_cr_fixed1_bits_update()
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