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/arch/m68k/ifpsp060/src/
Ditest.S72 link %a6,&-160
81 clr.l TESTCTR(%a6)
91 clr.l TESTCTR(%a6)
101 clr.l TESTCTR(%a6)
111 clr.l TESTCTR(%a6)
121 clr.l TESTCTR(%a6)
126 mov.l &0x2,EAMEM(%a6)
132 clr.l TESTCTR(%a6)
142 clr.l TESTCTR(%a6)
154 unlk %a6
[all …]
Dftest.S88 link %a6,&-384
98 clr.l TESTCTR(%a6)
108 clr.l TESTCTR(%a6)
118 clr.l TESTCTR(%a6)
126 clr.l TESTCTR(%a6)
136 unlk %a6
140 link %a6,&-384
150 clr.l TESTCTR(%a6)
162 unlk %a6
166 link %a6,&-384
[all …]
Disp.S482 btst &0x5,EXC_ISR(%a6) # supervisor mode?
484 btst &mia7_bit,SPCOND_FLG(%a6) # was a7 changed?
486 btst &0x7,EXC_ISR(%a6) # is trace enabled?
497 btst &mia7_bit,SPCOND_FLG(%a6) # was a7 changed?
500 btst &idbyz_bit,SPCOND_FLG(%a6) # did divide-by-zero occur?
504 btst &0x5,EXC_ISR(%a6) # supervisor mode?
512 btst &idbyz_bit,SPCOND_FLG(%a6) # did divide-by-zero occur?
514 tst.b EXC_ISR(%a6) # no; is trace enabled?
917 mov.w EXC_OPWORD(%a6),%d0 # fetch opcode word
1005 mov.l EXC_A0(%a6),%a0 # Get current a0
[all …]
Dpfpsp.S916 btst &0x4,1+EXC_CMDREG(%a6) # is op an fsincos?
919 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
922 lea FP_DST(%a6),%a0 # pass: ptr to dst op
928 mov.b %d0,DTAG(%a6) # save dst optype tag
932 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6)
933 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6)
934 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6)
935 #$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6)
936 #$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6)
937 #$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6)
[all …]
Dfplsp.S291 set EXC_A6, EXC_AREGS+(6*4) # offset of saved a6
563 link %a6,&-LOCAL_SIZE
565 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
566 fmovm.l %fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs
567 fmovm.x &0xc0,EXC_FP0(%a6) # save fp0/fp1
574 fmov.s 0x8(%a6),%fp0 # load sgl input
575 fmov.x %fp0,FP_SRC(%a6)
576 lea FP_SRC(%a6),%a0
578 mov.b %d0,STAG(%a6)
581 andi.l &0x00ff00ff,USER_FPSR(%a6)
[all …]
Dfpsp.S917 btst &0x4,1+EXC_CMDREG(%a6) # is op an fsincos?
920 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
923 lea FP_DST(%a6),%a0 # pass: ptr to dst op
929 mov.b %d0,DTAG(%a6) # save dst optype tag
933 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6)
934 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6)
935 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6)
936 #$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6)
937 #$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6)
938 #$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6)
[all …]
/arch/m68k/fpsp040/
Dscale.S52 movew FPTEMP(%a6),%d1 |get dest exponent
53 smi L_SCR1(%a6) |use L_SCR1 to hold sign
55 movew ETEMP(%a6),%d0 |check src bounds
66 moveb DTAG(%a6),%d0
70 st STORE_FLG(%a6) |dest already contains result
71 orl #unfl_mask,USER_FPSR(%a6) |set UNFL
73 leal FPTEMP(%a6),%a0
76 fmovel USER_FPCR(%a6),%FPCR
77 fmovex FPTEMP(%a6),%fp0 |simply return dest
86 fmovex ETEMP(%a6),%fp0 |move in src for int
[all …]
Dres_func.S53 clrb DNRM_FLG(%a6)
54 clrb RES_FLG(%a6)
55 clrb CU_ONLY(%a6)
56 tstb DY_MO_FLG(%a6)
59 btstb #7,DTAG(%a6) |if dop = norm=000, zero=001,
66 leal FPTEMP(%a6),%a0
77 bfclr DTAG(%a6){#0:#4} |set tag to normalized, FPTE15 = 0
78 bsetb #4,DTAG(%a6) |set FPTE15
79 orb #0x0f,DNRM_FLG(%a6)
81 leal ETEMP(%a6),%a0
[all …]
Dbugfix.S180 moveb CU_SAVEPC(%a6),%d0
193 movew CMDREG1B(%a6),%d0
200 bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src
201 bfextu CMDREG3B(%a6){#6:#3},%d1 |get 3rd dest
208 bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest
214 bfextu CMDREG2B(%a6){#6:#3},%d1 |get 2nd dest
217 bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src
225 bfextu CMDREG1B(%a6){#3:#3},%d0 |get source register no
230 fmovemx %d0,ETEMP(%a6) |load source to ETEMP
233 bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, extended
[all …]
Dx_unfl.S46 link %a6,#-LOCAL_SIZE
48 moveml %d0-%d1/%a0-%a1,USER_DA(%a6)
49 fmovemx %fp0-%fp3,USER_FP0(%a6)
50 fmoveml %fpcr/%fpsr/%fpiar,USER_FPCR(%a6)
58 btstb #unfl_bit,FPCR_ENABLE(%a6)
61 btstb #E3,E_BYTE(%a6)
67 bfextu CMDREG3B(%a6){#6:#3},%d0 |get dest reg no
68 bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit
70 movel USER_FPSR(%a6),FPSR_SHADOW(%a6)
71 orl #sx_mask,E_BYTE(%a6)
[all …]
Dget_op.S495 movew ETEMP(%a6),%d0 |get word with inf information
503 tstl ETEMP_HI(%a6) |check ms mantissa
505 tstl ETEMP_LO(%a6) |check ls mantissa
509 btstb #signan_bit,ETEMP_HI(%a6) |test for snan
511 orl #snaniop_mask,USER_FPSR(%a6) |always set snan if it is so
514 movew ETEMP_EX+2(%a6),%d0 |get word 4
518 tstl ETEMP_HI(%a6) |check words 3 and 2
520 tstl ETEMP_LO(%a6) |check words 1 and 0
522 tstl ETEMP(%a6) |test sign of the zero
524 movel #0x80000000,ETEMP(%a6) |write neg zero to etemp
[all …]
Dgen_except.S70 movel ETEMP_EX(%a6),ETEMP_EX(%a1) |copy etemp from unimp
71 movel ETEMP_HI(%a6),ETEMP_HI(%a1) |frame to busy frame
72 movel ETEMP_LO(%a6),ETEMP_LO(%a1)
73 movel CMDREG1B(%a6),CMDREG1B(%a1) |set inst in frame to unimp
74 movel CMDREG1B(%a6),%d0 |fix cmd1b to make it
76 bfextu CMDREG1B(%a6){#13:#1},%d1 |extract bit 2
80 bfextu CMDREG1B(%a6){#10:#3},%d1 |extract bit 3,4,5
89 orl %d0,USER_FPSR(%a6)
90 movel USER_FPSR(%a6),FPSR_SHADOW(%a1) |set exc bits
115 movel CMDREG1B(%a6),CMDREG1B(%a1) |set inst in frame to unimp
[all …]
Dx_operr.S145 tstl FPTEMP_LO(%a6)
147 cmpl #0xFFFFFFFF,FPTEMP_HI(%a6)
151 tstl FPTEMP_HI(%a6)
157 moveb STAG(%a6),%d0 |test stag for nan
161 cmpil #0xffff8000,FPTEMP_LO(%a6) |test if ls lword is special
173 movew FPTEMP_EX(%a6),%d0
177 movel FPTEMP_LO(%a6),%d0
184 moveb STAG(%a6),%d0 |test stag for nan
188 cmpil #0xffffff80,FPTEMP_LO(%a6) |test if ls lword is special
200 movew FPTEMP_EX(%a6),%d0
[all …]
Dx_snan.S43 link %a6,#-LOCAL_SIZE
45 moveml %d0-%d1/%a0-%a1,USER_DA(%a6)
46 fmovemx %fp0-%fp3,USER_FP0(%a6)
47 fmoveml %fpcr/%fpsr/%fpiar,USER_FPCR(%a6)
52 btstb #snan_bit,FPCR_ENABLE(%a6)
63 moveb FPCR_ENABLE(%a6),%d0
64 andb FPSR_EXCEPT(%a6),%d0
71 moveb #INEX_VEC,EXC_VEC+1(%a6)
72 moveml USER_DA(%a6),%d0-%d1/%a0-%a1
73 fmovemx USER_FP0(%a6),%fp0-%fp3
[all …]
Dx_fline.S47 link %a6,#-LOCAL_SIZE
49 moveml %d0-%d1/%a0-%a1,USER_DA(%a6)
50 moveal EXC_PC+4(%a6),%a0 |get address of fline instruction
51 leal L_SCR1(%a6),%a1 |use L_SCR1 as scratch
53 addl #4,%a6 |to offset the sub.l #4,a7 above so that
54 | ;a6 can point correctly to the stack frame
57 subl #4,%a6
58 movel L_SCR1(%a6),%d0 |d0 contains the fline and command word
83 movew EXC_SR+4(%a6),EXC_SR(%a6) |move stacked sr to new position
84 movel EXC_PC+4(%a6),EXC_PC(%a6) |move stacked pc to new position
[all …]
Dutil.S103 btstb #E3,E_BYTE(%a6) |check for nu exception
106 movew CMDREG3B(%a6),%d0 |get the command word
112 movew CMDREG3B(%a6),%d0 |get the command word again
121 movew CMDREG1B(%a6),%d0 |get command word
127 movew CMDREG1B(%a6),%d0 |again get the command word
152 bfextu FPCR_MODE(%a6){#0:#2},%d0 |set round precision
183 bfextu FPCR_MODE(%a6){#2:#2},%d1 |set round mode
193 bsetb #inf_bit,FPSR_CC(%a6)
203 orl #neginf_mask,USER_FPSR(%a6)
213 bsetb #neg_bit,FPSR_CC(%a6)
[all …]
Dkernel_ex.S67 bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR
69 btstb #dz_bit,FPCR_ENABLE(%a6) |test FPCR for dz exc enabled
74 btstb #dz_bit,FPCR_ENABLE(%a6) |test FPCR for dz exc enabled
79 btstb #sign_bit,ETEMP_EX(%a6) |check sign for neg or pos
84 bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR
89 orl #dzinf_mask,USER_FPSR(%a6) |set I,DZ,ADZ
95 btstb #sign_bit,ETEMP_EX(%a6) |check sign for neg or pos
97 bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR
99 orl #dzinf_mask,USER_FPSR(%a6) |set I,DZ,ADZ
100 st STORE_FLG(%a6)
[all …]
Dstanh.S86 fmovex %fp0,X(%a6)
89 movel %d0,X(%a6)
97 movel X(%a6),%d0
98 movel %d0,SGN(%a6)
101 movel %d0,X(%a6)
102 andl #0x80000000,SGN(%a6)
103 fmovex X(%a6),%fp0 | ...FP0 IS Y = 2|X|
113 movel SGN(%a6),%d0
114 fmovex %fp1,V(%a6)
115 eorl %d0,V(%a6)
[all …]
Dskeleton.S66 link %a6,#-LOCAL_SIZE
68 bclrb #E1,E_BYTE(%a6)
70 unlk %a6
103 link %a6,#-LOCAL_SIZE
108 btstb #E1,E_BYTE(%a6) |test for E1 set
114 unlk %a6
121 unlk %a6
128 unlk %a6
138 unlk %a6
142 link %a6,#-LOCAL_SIZE
[all …]
Dsrem_mod.S100 movel #0,Mod_Flag(%a6)
106 movel #1,Mod_Flag(%a6)
112 movew %d3,SignY(%a6)
157 movew %d0,SignX(%a6)
158 movew SignY(%a6),%d1
161 movew %d1,SignQ(%a6) | ...sign(Q) obtained
202 movel %d3,L_SCR1(%a6) | ...save biased expo(Y)
203 movel %d0,L_SCR2(%a6) |save d0
216 movel L_SCR2(%a6),%d0 |restore d0
266 movel L_SCR1(%a6),%d0 | ...new biased expo of R
[all …]
/arch/xtensa/lib/
Dmemcopy.S74 l8ui a6, a3, 0
76 s8i a6, a5, 0
93 l8ui a6, a3, 0
96 s8i a6, a5, 0
103 l8ui a6, a3, 0
107 s8i a6, a5, 0
138 l32i a6, a3, 0
140 s32i a6, a5, 0
141 l32i a6, a3, 8
144 s32i a6, a5, 8
[all …]
Dusercopy.S88 EX(10f) l8ui a6, a3, 0
90 EX(10f) s8i a6, a5, 0
98 EX(10f) l8ui a6, a3, 0
101 EX(10f) s8i a6, a5, 0
121 EX(10f) l8ui a6, a3, 0
123 EX(10f) s8i a6, a5, 0
147 EX(10f) l32i a6, a3, 0
149 EX(10f) s32i a6, a5, 0
150 EX(10f) l32i a6, a3, 8
153 EX(10f) s32i a6, a5, 8
[all …]
Dchecksum.S60 l32i a6, a2, 0
62 ONES_ADD(a4, a6)
64 l32i a6, a2, 8
66 ONES_ADD(a4, a6)
68 l32i a6, a2, 16
70 ONES_ADD(a4, a6)
72 l32i a6, a2, 24
74 ONES_ADD(a4, a6)
90 l32i a6, a2, 0
91 ONES_ADD(a4, a6)
[all …]
/arch/xtensa/boot/boot-redboot/
Dbootstrap.S116 ___flush_dcache_all a5 a6
120 ___invalidate_icache_all a5 a6
140 movi a6, _param_start
144 s32i a8, a6, 0
146 addi a6, a6, 4
151 movi a6, __bss_start
155 s32i a5, a6, 0
156 addi a6, a6, 4
157 blt a6, a7, 3b
176 movi a6, _image_start
[all …]
/arch/xtensa/kernel/
Dmcount.S38 xor a6, a0, a1
39 and a6, a6, a3
40 xor a6, a6, a1
41 addi a6, a6, -MCOUNT_INSN_SIZE

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