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Searched refs:c2 (Results 1 – 25 of 66) sorted by relevance

123

/arch/arm/include/asm/
Dkvm_hyp.h28 #define TTBR0 __ACCESS_CP15_64(0, c2)
29 #define TTBR1 __ACCESS_CP15_64(1, c2)
30 #define VTTBR __ACCESS_CP15_64(6, c2)
46 #define TTBCR __ACCESS_CP15(c2, 0, c0, 2)
47 #define HTCR __ACCESS_CP15(c2, 4, c0, 2)
48 #define VTCR __ACCESS_CP15(c2, 4, c1, 2)
54 #define HSR __ACCESS_CP15(c5, 4, c2, 0)
67 #define PRRR __ACCESS_CP15(c10, 0, c2, 0)
68 #define NMRR __ACCESS_CP15(c10, 0, c2, 1)
78 #define CNTP_CTL __ACCESS_CP15(c14, 0, c2, 1)
/arch/s390/boot/
Dstring.c10 unsigned char c1, c2; in strncmp() local
14 c2 = *ct++; in strncmp()
15 if (c1 != c2) in strncmp()
16 return c1 < c2 ? -1 : 1; in strncmp()
/arch/mips/include/asm/sibyte/
Dboard.h29 #define setleds(t0, t1, c0, c1, c2, c3) \
35 li t1, c2; \
40 #define setleds(t0, t1, c0, c1, c2, c3)
/arch/arm/include/asm/hardware/
Dcp14.h54 #define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2)
59 #define RCP14_DBGBVR2() MRC14(0, c0, c2, 4)
75 #define RCP14_DBGBCR2() MRC14(0, c0, c2, 5)
91 #define RCP14_DBGWVR2() MRC14(0, c0, c2, 6)
107 #define RCP14_DBGWCR2() MRC14(0, c0, c2, 7)
124 #define RCP14_DBGBXVR2() MRC14(0, c1, c2, 1)
139 #define RCP14_DBGOSSRR() MRC14(0, c1, c2, 4)
143 #define RCP14_DBGDSAR() MRC14(0, c2, c0, 0)
150 #define RCP14_DBGDEVID() MRC14(0, c7, c2, 7)
159 #define WCP14_DBGDSCRext(val) MCR14(val, 0, c0, c2, 2)
[all …]
/arch/arm/kvm/
Dinit.S65 mcrr p15, 4, rr_lo_hi(r2, r3), c2
69 mrc p15, 4, r0, c2, c0, 2 @ HTCR
72 mrc p15, 0, r1, c2, c0, 2 @ TTBCR
75 mcr p15, 4, r0, c2, c0, 2 @ HTCR
79 mrc p15, 0, r0, c10, c2, 0
80 mcr p15, 4, r0, c10, c2, 0
81 mrc p15, 0, r0, c10, c2, 1
82 mcr p15, 4, r0, c10, c2, 1
/arch/arm/mm/
Dpv-fixup-asm.S63 mrrc p15, 0, r4, r5, c2 @ read TTBR0
66 mcrr p15, 0, r4, r5, c2 @ write back TTBR0
67 mrrc p15, 1, r4, r5, c2 @ read TTBR1
70 mcrr p15, 1, r4, r5, c2 @ write back TTBR1
Dproc-v7-3level.S50 mcrr p15, 0, rpgdl, rpgdh, c2 @ set TTB 0
131 mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
135 mcrr p15, 1, \ttbr1, \tmp, c2 @ load TTBR1
Dproc-v6.S104 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
142 mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
164 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
165 mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
166 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
210 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
215 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
Dproc-v7-2level.S56 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
145 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register
150 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
Dproc-v7.S140 mrrc p15, 1, r5, r7, c2 @ TTB 1
142 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
144 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
165 mcrr p15, 0, r1, ip, c2 @ TTB 0
166 mcrr p15, 1, r5, r7, c2 @ TTB 1
170 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
171 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
173 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
176 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
177 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
[all …]
Dproc-sa1100.S53 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
108 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
148 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
191 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
Dproc-sa110.S45 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
92 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
137 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
Dproc-xscale.S69 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
75 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
91 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
93 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
95 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
97 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
475 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
552 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
Dproc-arm940.S304 mcr p15, 0, r3, c6, c2, 0 @ set area 2, ROM/FLASH
305 mcr p15, 0, r3, c6, c2, 1
308 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
309 mcr p15, 0, r0, c2, c0, 1
Dproc-arm740.S94 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
97 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
/arch/arm/boot/compressed/
Dstring.c93 unsigned char c1, c2; in strcmp() local
98 c2 = *ct++; in strcmp()
99 res = c1 - c2; in strcmp()
/arch/x86/boot/
Dstring.c66 unsigned char c1, c2; in strncmp() local
70 c2 = *ct++; in strncmp()
71 if (c1 != c2) in strncmp()
72 return c1 < c2 ? -1 : 1; in strncmp()
/arch/arm/kvm/hyp/
Dentry.S58 mrc p15, 4, r3, c5, c2, 0 @ HSR
84 mcrmi p15, 4, r3, c5, c2, 0 @ HSR
Dhyp-entry.S181 mrc p15, 4, r1, c5, c2, 0 @ HSR
190 mrrc p15, 6, r0, r2, c2
/arch/m68k/include/asm/
Dpage_mm.h76 m68k_fixup(%c2, 1b+2) in ___pa()
87 m68k_fixup(%c2, 1b+2) in __va()
/arch/arm/boot/dts/
Dqcom-ipq4019-ap.dk07.1-c2.dts8 compatible = "qcom,ipq4019-ap-dk07.1-c2";
/arch/unicore32/kernel/
Dhibernate_asm.S29 movc p0.c2, r0, #0
62 movc p0.c2, r0, #0
/arch/powerpc/platforms/86xx/
Dmpc8610_hpcd.c146 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \ argument
150 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
/arch/powerpc/crypto/
Daes-tab-4k.S49 .long R(75, b7, b7, c2), R(e1, fd, fd, 1c)
117 .long R(9f, c2, c2, 5d), R(bd, d3, d3, 6e)
141 .long R(c2, 61, 61, a3), R(6a, 35, 35, 5f)
180 .long R(75, c2, 89, 6a), R(f4, 8e, 79, 78)
192 .long R(b2, eb, 28, 07), R(2f, b5, c2, 03)
250 .long R(f6, 8d, 13, c2), R(90, d8, b8, e8)
285 .long R(38, 24, 34, 2c), R(c2, a3, 40, 5f)
/arch/arm/kernel/
Diwmmxt.S93 mrc p15, 0, r2, c2, c0, 0
219 mrc p15, 0, r2, c2, c0, 0
229 mrc p15, 0, r2, c2, c0, 0
341 mrc p15, 0, r1, c2, c0, 0

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