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Searched refs:clk_pll2 (Results 1 – 1 of 1) sorted by relevance

/arch/arm/mach-ep93xx/
Dclock.c83 static struct clk clk_pll2 = { variable
87 .parent = &clk_pll2,
218 INIT_CK(NULL, "pll2", &clk_pll2),
367 max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4); in calc_clk_div()
385 mclk = &clk_pll2; in calc_clk_div()
562 clk_pll2.rate = clk_xtali.rate; in ep93xx_clock_init()
564 clk_pll2.rate = calc_pll_rate(value); in ep93xx_clock_init()
566 clk_pll2.rate = 0; in ep93xx_clock_init()
569 clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1); in ep93xx_clock_init()
580 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000); in ep93xx_clock_init()