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/arch/mips/include/asm/netlogic/xlr/
Dflash.h37 #define FLASH_CSBASE_ADDR(cs) (cs) argument
38 #define FLASH_CSADDR_MASK(cs) (0x10 + (cs)) argument
39 #define FLASH_CSDEV_PARM(cs) (0x20 + (cs)) argument
40 #define FLASH_CSTIME_PARMA(cs) (0x30 + (cs)) argument
41 #define FLASH_CSTIME_PARMB(cs) (0x40 + (cs)) argument
48 #define FLASH_NAND_CLE(cs) (0x90 + (cs)) argument
49 #define FLASH_NAND_ALE(cs) (0xa0 + (cs)) argument
/arch/mips/bcm63xx/
Dcs.c24 static int is_valid_cs(unsigned int cs) in is_valid_cs() argument
26 if (cs > 6) in is_valid_cs()
35 int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size) in bcm63xx_set_cs_base() argument
40 if (!is_valid_cs(cs)) in bcm63xx_set_cs_base()
55 bcm_mpi_writel(val, MPI_CSBASE_REG(cs)); in bcm63xx_set_cs_base()
66 int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait, in bcm63xx_set_cs_timing() argument
72 if (!is_valid_cs(cs)) in bcm63xx_set_cs_timing()
76 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); in bcm63xx_set_cs_timing()
83 bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); in bcm63xx_set_cs_timing()
94 int bcm63xx_set_cs_param(unsigned int cs, u32 params) in bcm63xx_set_cs_param() argument
[all …]
Ddev-pcmcia.c69 static int __init config_pcmcia_cs(unsigned int cs, in config_pcmcia_cs() argument
74 ret = bcm63xx_set_cs_status(cs, 0); in config_pcmcia_cs()
76 ret = bcm63xx_set_cs_base(cs, base, size); in config_pcmcia_cs()
78 ret = bcm63xx_set_cs_status(cs, 1); in config_pcmcia_cs()
83 unsigned int cs; member
88 .cs = MPI_CS_PCMCIA_COMMON,
93 .cs = MPI_CS_PCMCIA_ATTR,
98 .cs = MPI_CS_PCMCIA_IO,
132 ret = config_pcmcia_cs(pcmcia_cs[i].cs, in bcm63xx_pcmcia_register()
/arch/mips/netlogic/xlr/
Dplatform-flash.c88 int cs; member
99 FLASH_NAND_CLE(nand_priv.cs), cmd); in xlr_nand_ctrl()
102 FLASH_NAND_ALE(nand_priv.cs), cmd); in xlr_nand_ctrl()
143 uint64_t flash_map_base, int cs, struct resource *res) in setup_flash_resource() argument
147 base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs)); in setup_flash_resource()
148 mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs)); in setup_flash_resource()
158 int cs, boot_nand, boot_nor; in xlr_flash_init() local
187 cs = 0; in xlr_flash_init()
190 nand_priv.cs = cs; in xlr_flash_init()
192 setup_flash_resource(flash_mmio, flash_map_base, cs, in xlr_flash_init()
[all …]
/arch/x86/kernel/
Dtime.c115 void clocksource_arch_init(struct clocksource *cs) in clocksource_arch_init() argument
117 if (cs->archdata.vclock_mode == VCLOCK_NONE) in clocksource_arch_init()
120 if (cs->archdata.vclock_mode > VCLOCK_MAX) { in clocksource_arch_init()
122 cs->name, cs->archdata.vclock_mode); in clocksource_arch_init()
123 cs->archdata.vclock_mode = VCLOCK_NONE; in clocksource_arch_init()
126 if (cs->mask != CLOCKSOURCE_MASK(64)) { in clocksource_arch_init()
128 cs->name, cs->mask); in clocksource_arch_init()
129 cs->archdata.vclock_mode = VCLOCK_NONE; in clocksource_arch_init()
/arch/mips/include/asm/mach-bcm63xx/
Dbcm63xx_cs.h5 int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size);
6 int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
8 int bcm63xx_set_cs_param(unsigned int cs, u32 flags);
9 int bcm63xx_set_cs_status(unsigned int cs, int enable);
/arch/m68k/lib/
Dmemset.c21 char *cs = s; in memset() local
22 *cs++ = c; in memset()
23 s = cs; in memset()
69 char *cs = s; in memset() local
70 *cs = c; in memset()
/arch/x86/lib/
Dstring_32.c95 int strcmp(const char *cs, const char *ct) in strcmp() argument
110 : "1" (cs), "2" (ct) in strcmp()
118 int strncmp(const char *cs, const char *ct, size_t count) in strncmp() argument
135 : "1" (cs), "2" (ct), "3" (count) in strncmp()
180 void *memchr(const void *cs, int c, size_t count) in memchr() argument
192 : "a" (c), "0" (cs), "1" (count) in memchr()
Dstrstr_32.c5 char *strstr(const char *cs, const char *ct) in strstr() argument
29 : "0" (0), "1" (0xffffffff), "2" (cs), "g" (ct) in strstr()
/arch/arm/boot/dts/
Dkeystone-k2l-evm.dts67 ti,cs-chipselect = <0>;
69 ti,cs-min-turnaround-ns = <12>;
70 ti,cs-read-hold-ns = <6>;
71 ti,cs-read-strobe-ns = <23>;
72 ti,cs-read-setup-ns = <9>;
73 ti,cs-write-hold-ns = <8>;
74 ti,cs-write-strobe-ns = <23>;
75 ti,cs-write-setup-ns = <8>;
Dkeystone-k2e-evm.dts94 ti,cs-chipselect = <0>;
96 ti,cs-min-turnaround-ns = <12>;
97 ti,cs-read-hold-ns = <6>;
98 ti,cs-read-strobe-ns = <23>;
99 ti,cs-read-setup-ns = <9>;
100 ti,cs-write-hold-ns = <8>;
101 ti,cs-write-strobe-ns = <23>;
102 ti,cs-write-setup-ns = <8>;
Domap3430-sdp.dts63 gpmc,cs-on-ns = <0>;
64 gpmc,cs-rd-off-ns = <186>;
65 gpmc,cs-wr-off-ns = <186>;
113 gpmc,cs-on-ns = <0>;
114 gpmc,cs-rd-off-ns = <36>;
115 gpmc,cs-wr-off-ns = <36>;
159 gpmc,cs-on-ns = <0>;
160 gpmc,cs-rd-off-ns = <84>;
161 gpmc,cs-wr-off-ns = <72>;
Dkeystone-k2hk-evm.dts111 ti,cs-chipselect = <0>;
113 ti,cs-min-turnaround-ns = <12>;
114 ti,cs-read-hold-ns = <6>;
115 ti,cs-read-strobe-ns = <23>;
116 ti,cs-read-setup-ns = <9>;
117 ti,cs-write-hold-ns = <8>;
118 ti,cs-write-strobe-ns = <23>;
119 ti,cs-write-setup-ns = <8>;
/arch/arm/mach-footbridge/
Ddc21285-timer.c23 static u64 cksrc_dc21285_read(struct clocksource *cs) in cksrc_dc21285_read() argument
25 return cs->mask - *CSR_TIMER2_VALUE; in cksrc_dc21285_read()
28 static int cksrc_dc21285_enable(struct clocksource *cs) in cksrc_dc21285_enable() argument
30 *CSR_TIMER2_LOAD = cs->mask; in cksrc_dc21285_enable()
36 static void cksrc_dc21285_disable(struct clocksource *cs) in cksrc_dc21285_disable() argument
/arch/arm/mach-imx/
Dmx27.h104 #define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10) argument
105 #define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs)) argument
106 #define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) argument
107 #define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) argument
Dmx31.h112 #define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10) argument
113 #define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs)) argument
114 #define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) argument
115 #define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) argument
/arch/x86/include/asm/
Dptrace.h46 unsigned short cs; member
84 unsigned long cs; member
129 return ((regs->cs & SEGMENT_RPL_MASK) | (regs->flags & X86_VM_MASK)) >= USER_RPL; in user_mode()
131 return !!(regs->cs & 3); in user_mode()
152 return regs->cs == __USER_CS; in user_64bit_mode()
155 return regs->cs == __USER_CS || regs->cs == pv_info.extra_user_64bit_cs; in user_64bit_mode()
220 if (offset == offsetof(struct pt_regs, cs) || in regs_get_register()
/arch/mips/kernel/
Dcsrc-bcm1480.c19 static u64 bcm1480_hpt_read(struct clocksource *cs) in bcm1480_hpt_read() argument
39 struct clocksource *cs = &bcm1480_clocksource; in sb1480_clocksource_init() local
45 clocksource_register_hz(cs, zbbus); in sb1480_clocksource_init()
Dcsrc-sb1250.c35 static u64 sb1250_hpt_read(struct clocksource *cs) in sb1250_hpt_read() argument
55 struct clocksource *cs = &bcm1250_clocksource; in sb1250_clocksource_init() local
68 clocksource_register_hz(cs, V_SCD_TIMER_FREQ); in sb1250_clocksource_init()
/arch/mips/cavium-octeon/
Docteon-platform.c928 int cs, bootbus; in octeon_prune_device_tree() local
950 for (cs = 0; cs < 8; cs++) { in octeon_prune_device_tree()
951 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); in octeon_prune_device_tree()
960 if (cs >= 7) { in octeon_prune_device_tree()
974 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); in octeon_prune_device_tree()
991 new_reg[0] = cpu_to_be32(cs); in octeon_prune_device_tree()
994 new_reg[3] = cpu_to_be32(cs + 1); in octeon_prune_device_tree()
1007 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); in octeon_prune_device_tree()
1008 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); in octeon_prune_device_tree()
1009 ranges[(cs * 5) + 4] = cpu_to_be32(region_size); in octeon_prune_device_tree()
[all …]
/arch/mips/txx9/generic/
Dmem_tx4927.c45 unsigned int cs = 0; in tx4927_process_sdccr() local
60 cs = 256 << sdccr_cs; in tx4927_process_sdccr()
64 return rs * cs * mw * bs; in tx4927_process_sdccr()
/arch/nios2/kernel/
Dtime.c48 struct clocksource cs; member
58 to_nios2_clksource(struct clocksource *cs) in to_nios2_clksource() argument
60 return container_of(cs, struct nios2_clocksource, cs); in to_nios2_clksource()
84 static u64 nios2_timer_read(struct clocksource *cs) in nios2_timer_read() argument
86 struct nios2_clocksource *nios2_cs = to_nios2_clksource(cs); in nios2_timer_read()
99 .cs = {
112 return nios2_timer_read(&nios2_cs.cs); in get_cycles()
295 ret = clocksource_register_hz(&nios2_cs.cs, freq); in nios2_clocksource_init()
/arch/mips/include/asm/mach-au1x00/
Dau1550_spi.h12 void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
13 void (*deactivate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
/arch/powerpc/boot/
Dcuboot-pq2.c81 int cs = cs_ranges_buf[i].csnum; in update_cs_ranges() local
82 if (cs >= ctrl_size / 8) in update_cs_ranges()
88 base = in_be32(&ctrl_addr[cs * 2]); in update_cs_ranges()
95 option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff; in update_cs_ranges()
101 out_be32(&ctrl_addr[cs * 2], 0); in update_cs_ranges()
102 out_be32(&ctrl_addr[cs * 2 + 1], in update_cs_ranges()
104 out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr); in update_cs_ranges()
/arch/x86/include/asm/xen/
Dinterface_32.h60 uint16_t cs; member
81 unsigned long cs; member
87 ((struct xen_callback){ .cs = (__cs), .eip = (unsigned long)(__eip) })

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