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Searched refs:hw (Results 1 – 25 of 273) sorted by relevance

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/arch/arm/mach-sa1100/
Dclock.c23 static int clk_gpio27_enable(struct clk_hw *hw) in clk_gpio27_enable() argument
39 static void clk_gpio27_disable(struct clk_hw *hw) in clk_gpio27_disable() argument
71 static unsigned long clk_mpll_recalc_rate(struct clk_hw *hw, in clk_mpll_recalc_rate() argument
95 struct clk_hw *hw; in sa11xx_clk_init() local
98 hw = clk_hw_register_fixed_rate(NULL, "clk32768", NULL, 0, 32768); in sa11xx_clk_init()
99 if (IS_ERR(hw)) in sa11xx_clk_init()
100 return PTR_ERR(hw); in sa11xx_clk_init()
102 clk_hw_register_clkdev(hw, NULL, "sa1100-rtc"); in sa11xx_clk_init()
104 hw = clk_hw_register_fixed_rate(NULL, "clk3686400", NULL, 0, 3686400); in sa11xx_clk_init()
105 if (IS_ERR(hw)) in sa11xx_clk_init()
[all …]
/arch/powerpc/perf/
Dcore-fsl-emb.c179 if (event->hw.state & PERF_HES_STOPPED) in fsl_emb_pmu_read()
188 prev = local64_read(&event->hw.prev_count); in fsl_emb_pmu_read()
190 val = read_pmc(event->hw.idx); in fsl_emb_pmu_read()
191 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); in fsl_emb_pmu_read()
196 local64_sub(delta, &event->hw.period_left); in fsl_emb_pmu_read()
300 if (event->hw.config & FSL_EMB_EVENT_RESTRICTED) in fsl_emb_pmu_add()
317 event->hw.idx = i; in fsl_emb_pmu_add()
322 if (event->hw.sample_period) { in fsl_emb_pmu_add()
323 s64 left = local64_read(&event->hw.period_left); in fsl_emb_pmu_add()
327 local64_set(&event->hw.prev_count, val); in fsl_emb_pmu_add()
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Dcore-book3s.c1055 if (event->hw.state & PERF_HES_STOPPED) in power_pmu_read()
1058 if (!event->hw.idx) in power_pmu_read()
1062 val = read_pmc(event->hw.idx); in power_pmu_read()
1063 local64_set(&event->hw.prev_count, val); in power_pmu_read()
1073 prev = local64_read(&event->hw.prev_count); in power_pmu_read()
1075 val = read_pmc(event->hw.idx); in power_pmu_read()
1079 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); in power_pmu_read()
1093 prev = local64_read(&event->hw.period_left); in power_pmu_read()
1097 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); in power_pmu_read()
1120 if (!event->hw.idx) in freeze_limited_counters()
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/arch/arm/mm/
Dcache-l2x0-pmu.c119 struct hw_perf_event *hw = &event->hw; in l2x0_pmu_event_read() local
123 prev_count = local64_read(&hw->prev_count); in l2x0_pmu_event_read()
124 new_count = l2x0_pmu_counter_read(hw->idx); in l2x0_pmu_event_read()
125 } while (local64_xchg(&hw->prev_count, new_count) != prev_count); in l2x0_pmu_event_read()
135 struct hw_perf_event *hw = &event->hw; in l2x0_pmu_event_configure() local
147 local64_set(&hw->prev_count, 0); in l2x0_pmu_event_configure()
148 l2x0_pmu_counter_write(hw->idx, 0); in l2x0_pmu_event_configure()
188 struct hw_perf_event *hw = &event->hw; in l2x0_pmu_event_start() local
190 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) in l2x0_pmu_event_start()
194 WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE)); in l2x0_pmu_event_start()
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/arch/mips/alchemy/common/
Dclock.c118 static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw, in alchemy_clk_cpu_recalc() argument
173 struct clk_hw hw; member
177 #define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
179 static unsigned long alchemy_clk_aux_recalc(struct clk_hw *hw, in alchemy_clk_aux_recalc() argument
182 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw); in alchemy_clk_aux_recalc()
187 static int alchemy_clk_aux_setr(struct clk_hw *hw, in alchemy_clk_aux_setr() argument
191 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw); in alchemy_clk_aux_setr()
207 static long alchemy_clk_aux_roundr(struct clk_hw *hw, in alchemy_clk_aux_roundr() argument
211 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw); in alchemy_clk_aux_roundr()
253 a->hw.init = &id; in alchemy_clk_setup_aux()
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/arch/x86/kernel/
Dhw_breakpoint.c214 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) in arch_check_bp_in_kernelspace() argument
219 va = hw->address; in arch_check_bp_in_kernelspace()
220 len = arch_bp_generic_len(hw->len); in arch_check_bp_in_kernelspace()
232 struct arch_hw_breakpoint *hw) in arch_build_bp_info() argument
234 hw->address = attr->bp_addr; in arch_build_bp_info()
235 hw->mask = 0; in arch_build_bp_info()
240 hw->type = X86_BREAKPOINT_WRITE; in arch_build_bp_info()
243 hw->type = X86_BREAKPOINT_RW; in arch_build_bp_info()
256 hw->type = X86_BREAKPOINT_EXECUTE; in arch_build_bp_info()
263 hw->len = X86_BREAKPOINT_LEN_X; in arch_build_bp_info()
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/arch/sh/kernel/
Dhw_breakpoint.c124 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) in arch_check_bp_in_kernelspace() argument
129 va = hw->address; in arch_check_bp_in_kernelspace()
130 len = get_hbp_len(hw->len); in arch_check_bp_in_kernelspace()
176 struct arch_hw_breakpoint *hw) in arch_build_bp_info() argument
178 hw->address = attr->bp_addr; in arch_build_bp_info()
183 hw->len = SH_BREAKPOINT_LEN_1; in arch_build_bp_info()
186 hw->len = SH_BREAKPOINT_LEN_2; in arch_build_bp_info()
189 hw->len = SH_BREAKPOINT_LEN_4; in arch_build_bp_info()
192 hw->len = SH_BREAKPOINT_LEN_8; in arch_build_bp_info()
201 hw->type = SH_BREAKPOINT_READ; in arch_build_bp_info()
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Dperf_event.c121 struct hw_perf_event *hwc = &event->hw; in __hw_perf_event_init()
220 struct hw_perf_event *hwc = &event->hw; in sh_pmu_stop()
223 if (!(event->hw.state & PERF_HES_STOPPED)) { in sh_pmu_stop()
226 event->hw.state |= PERF_HES_STOPPED; in sh_pmu_stop()
229 if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) { in sh_pmu_stop()
230 sh_perf_event_update(event, &event->hw, idx); in sh_pmu_stop()
231 event->hw.state |= PERF_HES_UPTODATE; in sh_pmu_stop()
238 struct hw_perf_event *hwc = &event->hw; in sh_pmu_start()
245 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); in sh_pmu_start()
248 event->hw.state = 0; in sh_pmu_start()
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/arch/arm/mach-omap2/
Dclkt2xxx_virt_prcm_set.c71 long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, in omap2_round_to_table_rate() argument
95 int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, in omap2_select_table_rate() argument
229 struct clk_hw_omap *hw = NULL; in omap2xxx_clkt_vps_init() local
236 hw = kzalloc(sizeof(*hw), GFP_KERNEL); in omap2xxx_clkt_vps_init()
237 if (!hw) in omap2xxx_clkt_vps_init()
244 hw->hw.init = &init; in omap2xxx_clkt_vps_init()
246 clk = clk_register(NULL, &hw->hw); in omap2xxx_clkt_vps_init()
250 kfree(hw); in omap2xxx_clkt_vps_init()
Dclock2xxx.h17 int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
19 long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
25 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
Dclkt2xxx_dpllcore.c102 unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, in omap2_dpllcore_recalc() argument
108 int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, in omap2_reprogram_dpllcore() argument
111 struct clk_hw_omap *clk = to_clk_hw_omap(hw); in omap2_reprogram_dpllcore()
189 void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw) in omap2xxx_clkt_dpllcore_init() argument
192 dpll_core_ck = to_clk_hw_omap(hw); in omap2xxx_clkt_dpllcore_init()
/arch/arm64/kernel/
Dhw_breakpoint.c162 struct task_struct *tsk = bp->hw.target; in is_compat_bp()
335 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) in arch_check_bp_in_kernelspace() argument
340 va = hw->address; in arch_check_bp_in_kernelspace()
341 len = get_hbp_len(hw->ctrl.len); in arch_check_bp_in_kernelspace()
414 struct arch_hw_breakpoint *hw) in arch_build_bp_info() argument
419 hw->ctrl.type = ARM_BREAKPOINT_EXECUTE; in arch_build_bp_info()
422 hw->ctrl.type = ARM_BREAKPOINT_LOAD; in arch_build_bp_info()
425 hw->ctrl.type = ARM_BREAKPOINT_STORE; in arch_build_bp_info()
428 hw->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; in arch_build_bp_info()
437 hw->ctrl.len = ARM_BREAKPOINT_LEN_1; in arch_build_bp_info()
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/arch/xtensa/kernel/
Dhw_breakpoint.c36 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) in arch_check_bp_in_kernelspace() argument
41 va = hw->address; in arch_check_bp_in_kernelspace()
42 len = hw->len; in arch_check_bp_in_kernelspace()
52 struct arch_hw_breakpoint *hw) in hw_breakpoint_arch_parse() argument
57 hw->type = XTENSA_BREAKPOINT_EXECUTE; in hw_breakpoint_arch_parse()
60 hw->type = XTENSA_BREAKPOINT_LOAD; in hw_breakpoint_arch_parse()
63 hw->type = XTENSA_BREAKPOINT_STORE; in hw_breakpoint_arch_parse()
66 hw->type = XTENSA_BREAKPOINT_LOAD | XTENSA_BREAKPOINT_STORE; in hw_breakpoint_arch_parse()
73 hw->len = attr->bp_len; in hw_breakpoint_arch_parse()
74 if (hw->len < 1 || hw->len > 64 || !is_power_of_2(hw->len)) in hw_breakpoint_arch_parse()
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Dperf_event.c144 new_raw_count = xtensa_pmu_read_counter(event->hw.idx); in xtensa_perf_event_update()
207 event->hw.config = xtensa_hw_ctl[event->attr.config]; in xtensa_pmu_event_init()
214 event->hw.config = ret; in xtensa_pmu_event_init()
222 event->hw.config = (event->attr.config & in xtensa_pmu_event_init()
242 struct hw_perf_event *hwc = &event->hw; in xtensa_pmu_start()
249 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); in xtensa_pmu_start()
260 struct hw_perf_event *hwc = &event->hw; in xtensa_pmu_stop()
271 !(event->hw.state & PERF_HES_UPTODATE)) { in xtensa_pmu_stop()
272 xtensa_perf_event_update(event, &event->hw, idx); in xtensa_pmu_stop()
273 event->hw.state |= PERF_HES_UPTODATE; in xtensa_pmu_stop()
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/arch/powerpc/kernel/
Dhw_breakpoint.c112 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) in arch_check_bp_in_kernelspace() argument
114 return is_kernel_addr(hw->address); in arch_check_bp_in_kernelspace()
134 struct arch_hw_breakpoint *hw) in hw_breakpoint_arch_parse() argument
141 hw->type = HW_BRK_TYPE_TRANSLATE; in hw_breakpoint_arch_parse()
143 hw->type |= HW_BRK_TYPE_READ; in hw_breakpoint_arch_parse()
145 hw->type |= HW_BRK_TYPE_WRITE; in hw_breakpoint_arch_parse()
146 if (hw->type == HW_BRK_TYPE_TRANSLATE) in hw_breakpoint_arch_parse()
150 hw->type |= HW_BRK_TYPE_USER; in hw_breakpoint_arch_parse()
152 hw->type |= HW_BRK_TYPE_KERNEL; in hw_breakpoint_arch_parse()
154 hw->type |= HW_BRK_TYPE_HYP; in hw_breakpoint_arch_parse()
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/arch/arm/kernel/
Dhw_breakpoint.c448 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) in arch_check_bp_in_kernelspace() argument
453 va = hw->address; in arch_check_bp_in_kernelspace()
454 len = get_hbp_len(hw->ctrl.len); in arch_check_bp_in_kernelspace()
511 struct arch_hw_breakpoint *hw) in arch_build_bp_info() argument
516 hw->ctrl.type = ARM_BREAKPOINT_EXECUTE; in arch_build_bp_info()
519 hw->ctrl.type = ARM_BREAKPOINT_LOAD; in arch_build_bp_info()
522 hw->ctrl.type = ARM_BREAKPOINT_STORE; in arch_build_bp_info()
525 hw->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; in arch_build_bp_info()
534 hw->ctrl.len = ARM_BREAKPOINT_LEN_1; in arch_build_bp_info()
537 hw->ctrl.len = ARM_BREAKPOINT_LEN_2; in arch_build_bp_info()
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Dbios32.c454 static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, in pcibios_init_hw() argument
461 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) { in pcibios_init_hw()
471 sys->swizzle = hw->swizzle; in pcibios_init_hw()
472 sys->map_irq = hw->map_irq; in pcibios_init_hw()
475 if (hw->private_data) in pcibios_init_hw()
476 sys->private_data = hw->private_data[nr]; in pcibios_init_hw()
478 ret = hw->setup(nr, sys); in pcibios_init_hw()
482 ret = pcibios_init_resource(nr, sys, hw->io_optional); in pcibios_init_hw()
491 if (hw->scan) in pcibios_init_hw()
492 ret = hw->scan(nr, bridge); in pcibios_init_hw()
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/arch/s390/kernel/
Dperf_cpum_cf.c205 struct hw_perf_event *hwc = &event->hw; in __hw_perf_event_init()
320 prev = local64_read(&event->hw.prev_count); in hw_perf_event_reset()
321 err = ecctr(event->hw.config, &new); in hw_perf_event_reset()
332 } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev); in hw_perf_event_reset()
343 prev = local64_read(&event->hw.prev_count); in hw_perf_event_update()
344 err = ecctr(event->hw.config, &new); in hw_perf_event_update()
347 } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev); in hw_perf_event_update()
356 if (event->hw.state & PERF_HES_STOPPED) in cpumf_pmu_read()
365 struct hw_perf_event *hwc = &event->hw; in cpumf_pmu_start()
396 struct hw_perf_event *hwc = &event->hw; in cpumf_pmu_stop()
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Dperf_cpum_cf_diag.c207 event->hw.config = attr->config; in __hw_perf_event_init()
208 event->hw.config_base = 0; in __hw_perf_event_init()
221 event->hw.config_base |= cpumf_ctr_ctl[i]; in __hw_perf_event_init()
225 if (!event->hw.config_base) { in __hw_perf_event_init()
231 event->hw.sample_period = attr->sample_period; in __hw_perf_event_init()
232 local64_set(&event->hw.period_left, event->hw.sample_period); in __hw_perf_event_init()
233 event->hw.last_period = event->hw.sample_period; in __hw_perf_event_init()
236 __func__, err, event->hw.config_base); in __hw_perf_event_init()
496 perf_sample_data_init(&data, 0, event->hw.last_period); in cf_diag_push_sample()
525 struct hw_perf_event *hwc = &event->hw; in cf_diag_start()
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/arch/x86/events/
Dmsr.c207 event->hw.idx = -1; in msr_event_init()
208 event->hw.event_base = msr[cfg].msr; in msr_event_init()
209 event->hw.config = cfg; in msr_event_init()
218 if (event->hw.event_base) in msr_read_counter()
219 rdmsrl(event->hw.event_base, now); in msr_read_counter()
233 prev = local64_read(&event->hw.prev_count); in msr_event_update()
236 if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev) in msr_event_update()
240 if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) { in msr_event_update()
243 } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) { in msr_event_update()
256 local64_set(&event->hw.prev_count, now); in msr_event_start()
/arch/c6x/kernel/
Dirq.c74 irq_hw_number_t hw) in core_domain_map() argument
76 if (hw < 4 || hw >= NR_PRIORITY_IRQS) in core_domain_map()
79 prio_to_virq[hw] = virq; in core_domain_map()
/arch/alpha/kernel/
Dperf_event.c199 event[0]->hw.idx = idx0; in ev67_check_constraints()
200 event[0]->hw.config_base = config; in ev67_check_constraints()
202 event[1]->hw.idx = idx0 ^ 1; in ev67_check_constraints()
203 event[1]->hw.config_base = config; in ev67_check_constraints()
351 evtype[n] = group->hw.event_base; in collect_events()
359 evtype[n] = pe->hw.event_base; in collect_events()
403 cpuc->current_idx[j] != pe->hw.idx) { in maybe_change_configuration()
404 alpha_perf_event_update(pe, &pe->hw, cpuc->current_idx[j], 0); in maybe_change_configuration()
413 struct hw_perf_event *hwc = &pe->hw; in maybe_change_configuration()
424 cpuc->config = cpuc->event[0]->hw.config_base; in maybe_change_configuration()
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/arch/x86/events/amd/
Dpower.c49 struct hw_perf_event *hwc = &event->hw; in event_update()
77 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) in __pmu_event_start()
80 event->hw.state = 0; in __pmu_event_start()
82 rdmsrl(MSR_F15H_PTSC, event->hw.ptsc); in __pmu_event_start()
83 rdmsrl(MSR_F15H_CU_PWR_ACCUMULATOR, event->hw.pwr_acc); in __pmu_event_start()
93 struct hw_perf_event *hwc = &event->hw; in pmu_event_stop()
112 struct hw_perf_event *hwc = &event->hw; in pmu_event_add()
/arch/nios2/
DMakefile29 KBUILD_CFLAGS += $(if $(CONFIG_NIOS2_HW_MUL_SUPPORT),-mhw-mul,-mno-hw-mul)
30 KBUILD_CFLAGS += $(if $(CONFIG_NIOS2_HW_MULX_SUPPORT),-mhw-mulx,-mno-hw-mulx)
31 KBUILD_CFLAGS += $(if $(CONFIG_NIOS2_HW_DIV_SUPPORT),-mhw-div,-mno-hw-div)
/arch/arc/kernel/
Dperf_event.c136 arc_perf_event_update(event, &event->hw, event->hw.idx); in arc_pmu_read()
169 struct hw_perf_event *hwc = &event->hw; in arc_pmu_event_init()
245 struct hw_perf_event *hwc = &event->hw; in arc_pmu_event_set_period()
291 struct hw_perf_event *hwc = &event->hw; in arc_pmu_start()
316 struct hw_perf_event *hwc = &event->hw; in arc_pmu_stop()
330 if (!(event->hw.state & PERF_HES_STOPPED)) { in arc_pmu_stop()
337 event->hw.state |= PERF_HES_STOPPED; in arc_pmu_stop()
341 !(event->hw.state & PERF_HES_UPTODATE)) { in arc_pmu_stop()
342 arc_perf_event_update(event, &event->hw, idx); in arc_pmu_stop()
343 event->hw.state |= PERF_HES_UPTODATE; in arc_pmu_stop()
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