Home
last modified time | relevance | path

Searched refs:instruction (Results 1 – 25 of 120) sorted by relevance

12345

/arch/sh/kernel/
Dtraps_32.c85 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, in handle_unaligned_ins() argument
93 index = (instruction>>8)&15; /* 0x0F00 */ in handle_unaligned_ins()
96 index = (instruction>>4)&15; /* 0x00F0 */ in handle_unaligned_ins()
99 count = 1<<(instruction&3); in handle_unaligned_ins()
109 switch (instruction>>12) { in handle_unaligned_ins()
111 if (instruction & 8) { in handle_unaligned_ins()
143 dstu += (instruction&0x000F)<<2; in handle_unaligned_ins()
151 if (instruction & 4) in handle_unaligned_ins()
165 srcu += (instruction & 0x000F) << 2; in handle_unaligned_ins()
176 if (instruction & 4) in handle_unaligned_ins()
[all …]
Dio_trapped.c271 insn_size_t instruction; in handle_trapped_io() local
283 if (copy_from_user(&instruction, (void *)(regs->pc), in handle_trapped_io()
284 sizeof(instruction))) { in handle_trapped_io()
289 tmp = handle_unaligned_access(instruction, regs, in handle_trapped_io()
/arch/nios2/platform/
DKconfig.platform63 bool "Enable MUL instruction"
66 instruction. This will enable the -mhw-mul compiler flag.
69 bool "Enable MULX instruction"
72 instruction. Enables the -mhw-mulx compiler flag.
75 bool "Enable DIV instruction"
78 instruction. Enables the -mhw-div compiler flag.
102 bool "Byteswap custom instruction"
104 Use the byteswap (endian converter) Nios II custom instruction provided
109 int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT
112 Number of the instruction as configured in QSYS Builder.
[all …]
/arch/m68k/fpsp040/
Dsmovecr.S5 | offset given in the instruction field.
7 | Input: An offset in the instruction word.
Dbugfix.S247 | dest and the dest of the xu. We must clear the instruction in
248 | the cu and restore the state, allowing the instruction in the
249 | xu to complete. Remember, the instruction in the nu
251 | If the result of the xu instruction is not exceptional, we can
252 | restore the instruction from the cu to the frame and continue
275 | Check if the instruction which just completed was exceptional.
280 | It is necessary to isolate the result of the instruction in the
369 | dest and the dest of the xu. We must clear the instruction in
370 | the cu and restore the state, allowing the instruction in the
371 | xu to complete. Remember, the instruction in the nu
[all …]
/arch/arm/nwfpe/
Dentry.S78 bne next @ get the next instruction;
81 bl EmulateAll @ emulate the instruction
87 .Lx1: ldrt r6, [r5], #4 @ get the next instruction and
104 @ plain LDR instruction. Weird, but it seems harmless.
Dfpmodule.inl24 /* Note: The CPU thinks it has dealt with the current instruction.
26 instruction, and points 4 bytes beyond the actual instruction
27 that caused the invalid instruction trap to occur. We adjust
/arch/arm/probes/kprobes/
Dtest-core.h154 #define TEST_INSTRUCTION(instruction) \ argument
156 "1: "instruction" \n\t" \
159 #define TEST_BRANCH_F(instruction) \ argument
160 TEST_INSTRUCTION(instruction) \
164 #define TEST_BRANCH_B(instruction) \ argument
169 TEST_INSTRUCTION(instruction)
171 #define TEST_BRANCH_FX(instruction, codex) \ argument
172 TEST_INSTRUCTION(instruction) \
178 #define TEST_BRANCH_BX(instruction, codex) \ argument
184 TEST_INSTRUCTION(instruction)
/arch/openrisc/
DKconfig98 bool "Have instruction l.ff1"
101 Select this if your implementation has the Class II instruction l.ff1
104 bool "Have instruction l.fl1"
107 Select this if your implementation has the Class II instruction l.fl1
110 bool "Have instruction l.mul for hardware multiply"
113 Select this if your implementation has a hardware multiply instruction
116 bool "Have instruction l.div for hardware divide"
119 Select this if your implementation has a hardware divide instruction
/arch/s390/kvm/
Dtrace.h157 __field(__u64, instruction)
162 __entry->instruction = ((__u64)ipa << 48) |
167 __entry->instruction,
168 __print_symbolic(icpt_insn_decoder(__entry->instruction),
424 __field(__u64, instruction)
429 __entry->instruction = ((__u64)ipa << 48) |
434 __entry->instruction,
435 __print_symbolic(icpt_insn_decoder(__entry->instruction),
/arch/xtensa/
DKconfig.debug25 bool "Perform S32C1I instruction self-test at boot"
28 Enable this option to test S32C1I instruction behavior at boot.
29 Correct operation of this instruction requires some cooperation from hardware
/arch/arm/kernel/
Dentry-armv.S240 @ Correct the PC such that it is pointing at the instruction
241 @ which caused the fault. If the faulting instruction was ARM
242 @ the PC will be pointing at the next instruction, and have to
244 @ pointing at the second half of the Thumb instruction. We
255 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
264 @ the instruction, or the more conventional lr if we are to treat
265 @ this as a real undefined instruction
267 @ r0 - instruction
273 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
274 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
[all …]
/arch/mips/loongson64/
DPlatform29 # an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction
34 # instruction that labels refer to, ie. if we label an ll instruction:
39 # instruction inserted by the assembler, and if we were using the label in an
41 # instruction.
/arch/powerpc/kernel/
Dmodule_64.c453 static bool is_mprofile_mcount_callsite(const char *name, u32 *instruction) in is_mprofile_mcount_callsite() argument
461 if (instruction[-1] == PPC_INST_STD_LR && in is_mprofile_mcount_callsite()
462 instruction[-2] == PPC_INST_MFLR) in is_mprofile_mcount_callsite()
465 if (instruction[-1] == PPC_INST_MFLR) in is_mprofile_mcount_callsite()
489 static bool is_mprofile_mcount_callsite(const char *name, u32 *instruction) in is_mprofile_mcount_callsite() argument
497 static int restore_r2(const char *name, u32 *instruction, struct module *me) in restore_r2() argument
499 u32 *prev_insn = instruction - 1; in restore_r2()
512 if (*instruction != PPC_INST_NOP) { in restore_r2()
514 me->name, *instruction, instruction); in restore_r2()
518 *instruction = PPC_INST_LD_TOC; in restore_r2()
/arch/m68k/ifpsp060/src/
Disp.S1218 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1219 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1230 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1231 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1242 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1243 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1254 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1255 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1266 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1267 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
[all …]
Dpfpsp.S1228 # the FPIAR holds the "current PC" of the faulting instruction
1232 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1233 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
1234 bsr.l _imem_read_long # fetch the instruction words
1722 # three instruction exceptions don't update the stack pointer. so, if the
2038 # The opclass two PACKED instruction that took an "Unimplemented Data Type"
2371 # _imem_read_long() - read instruction longword #
2384 # fmovm_dynamic() - emulate dynamic fmovm instruction #
2385 # fmovm_ctrl() - emulate fmovm control instruction #
2404 # (2) The "fmovm.x" instruction w/ dynamic register specification. #
[all …]
/arch/mips/bcm47xx/
DKconfig20 This will generate an image with support for SSB and MIPS32 R1 instruction set.
36 This will generate an image with support for BCMA and MIPS32 R2 instruction set.
/arch/ia64/scripts/
Dcheck-serialize.S2 .serialize.instruction
/arch/arm/vfp/
Dentry.S17 @ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
21 @ lr = unrecognised instruction return address
/arch/m68k/ifpsp060/
DCHANGES41 3) For an opclass three FP instruction where the effective addressing
62 next instruction, and the result created in fp0 will be
78 For instruction read access errors, the info stacked is:
80 PC = PC of instruction being emulated
82 ADDRESS = PC of instruction being emulated
102 PC = PC of instruction being emulated
Dilsp.doc35 and the "cmp2" instruction. These instructions are not
71 function. A branch instruction located at the selected entry point
78 For example, to use a 64-bit multiply instruction,
115 An example of using the "cmp2" instruction is as follows:
128 If the instruction being emulated is a divide and the source
130 instruction, executes an implemented divide using a zero
133 point to the correct instruction, the user will at least be able
/arch/powerpc/xmon/
Dppc.h263 (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
284 long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
/arch/unicore32/mm/
DKconfig5 # which CPUs we support in the kernel image, and the compiler instruction
16 Say Y here to disable the processor instruction cache. Unless
/arch/mips/dec/prom/
Dlocore.S27 addiu k0, 4 # skip the causing instruction
/arch/s390/kernel/
Dmcount.S63 # The j instruction gets runtime patched to a nop instruction.

12345