Searched refs:microcode (Results 1 – 21 of 21) sorted by relevance
| /arch/x86/kernel/cpu/microcode/ |
| D | Makefile | 2 microcode-y := core.o
3 obj-$(CONFIG_MICROCODE) += microcode.o
4 microcode-$(CONFIG_MICROCODE_INTEL) += intel.o
5 microcode-$(CONFIG_MICROCODE_AMD) += amd.o
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| D | intel.c | 778 csig->rev = c->microcode; in collect_cpu_info()
852 c->microcode = rev; in apply_microcode_intel()
856 boot_cpu_data.microcode = rev; in apply_microcode_intel()
959 c->microcode < 0x0b000021) { in is_blacklisted()
960 …rr_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode); in is_blacklisted()
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| D | amd.c | 654 csig->rev = c->microcode; in collect_cpu_info_amd()
710 c->microcode = rev; in apply_microcode_amd()
714 boot_cpu_data.microcode = rev; in apply_microcode_amd()
856 if (boot_cpu_data.microcode >= p->patch_id) in load_microcode_amd()
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| D | core.c | 608 pr_info("Reload completed, microcode revision: 0x%x\n", boot_cpu_data.microcode); in microcode_reload_late()
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| /arch/x86/include/uapi/asm/ |
| D | mce.h | 37 __u32 microcode; /* Microcode revision */ member
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| /arch/x86/kernel/cpu/ |
| D | proc.c | 79 if (c->microcode) in show_cpuinfo()
80 seq_printf(m, "microcode\t: 0x%x\n", c->microcode); in show_cpuinfo()
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| D | match.c | 76 if (!res || res->x86_microcode_rev > boot_cpu_data.microcode) in x86_cpu_has_min_microcode_rev()
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| D | intel.c | 142 u32 microcode; member
185 return (c->microcode <= spectre_bad_microcodes[i].microcode); in bad_spectre_microcode()
208 c->microcode = intel_get_microcode_revision(); in early_init_intel()
235 c->microcode < 0x20e) { in early_init_intel()
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| D | Makefile | 46 obj-$(CONFIG_MICROCODE) += microcode/
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| D | hygon.c | 268 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); in early_init_hygon()
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| D | amd.c | 639 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); in early_init_amd()
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| /arch/x86/kernel/cpu/mce/ |
| D | inject.c | 104 m->microcode = boot_cpu_data.microcode; in setup_inj_struct()
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| D | core.c | 148 m->microcode = boot_cpu_data.microcode; in mce_setup()
281 m->microcode); in __print_mce()
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| /arch/x86/ |
| D | Kconfig | 1309 bool "CPU microcode loading support"
1314 If you say Y here, you will be able to update the microcode on
1318 the actual microcode binary data itself which is not shipped with
1321 The preferred method to load microcode from a detached initrd is described
1322 in Documentation/x86/microcode.rst. For that you need to enable
1324 initrd for microcode blobs.
1326 In addition, you can build the microcode into the kernel. For that you
1327 need to add the vendor-supplied microcode to the CONFIG_EXTRA_FIRMWARE
1331 bool "Intel microcode loading support"
1336 This options enables microcode patch loading support for Intel
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| /arch/powerpc/platforms/8xx/ |
| D | Kconfig | 163 This microcode relocates SMC1 and SMC2 parameter RAMs at
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| /arch/powerpc/boot/dts/fsl/ |
| D | p1021rdb-pc.dtsi | 74 label = "NOR QE microcode firmware";
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| D | p1021mds.dts | 80 /* 1MB for microcode */
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| D | p1025twr.dtsi | 81 label = "NOR QE microcode firmware";
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| /arch/x86/include/asm/ |
| D | processor.h | 124 u32 microcode; member
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| /arch/x86/kernel/apic/ |
| D | apic.c | 634 if (boot_cpu_data.microcode >= rev) in apic_check_deadline_errata()
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| /arch/m68k/fpsp040/ |
| D | res_func.S | 1968 | the 040 uses the dtag to execute the correct microcode.
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