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Searched refs:pll1_div (Results 1 – 1 of 1) sorted by relevance

/arch/sh/kernel/cpu/sh2a/
Dclock-sh7264.c26 static unsigned int pll1_div; variable
43 unsigned long rate = clk->parent->rate / pll1_div; in pll_recalc()
139 pll1_div = 3; in arch_clk_init()
141 pll1_div = 4; in arch_clk_init()
143 pll1_div = 1; in arch_clk_init()