/arch/powerpc/sysdev/ |
D | ipic.c | 35 .prio = IPIC_SIPRR_C, 42 .prio = IPIC_SIPRR_C, 49 .prio = IPIC_SIPRR_C, 56 .prio = IPIC_SIPRR_C, 63 .prio = IPIC_SIPRR_C, 70 .prio = IPIC_SIPRR_C, 77 .prio = IPIC_SIPRR_C, 84 .prio = IPIC_SIPRR_C, 91 .prio = IPIC_SIPRR_D, 98 .prio = IPIC_SIPRR_D, [all …]
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D | ehv_pic.c | 74 unsigned int config, prio, cpu_dest; in ehv_pic_set_affinity() local 79 ev_int_get_config(src, &config, &prio, &cpu_dest); in ehv_pic_set_affinity() 80 ev_int_set_config(src, config, prio, cpuid); in ehv_pic_set_affinity() 114 unsigned int vecpri, vold, vnew, prio, cpu_dest; in ehv_pic_set_irq_type() local 125 ev_int_get_config(src, &vold, &prio, &cpu_dest); in ehv_pic_set_irq_type() 136 prio = 8; in ehv_pic_set_irq_type() 138 ev_int_set_config(src, vecpri, prio, cpu_dest); in ehv_pic_set_irq_type()
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/arch/powerpc/sysdev/xive/ |
D | spapr.c | 194 unsigned long prio, in plpar_int_set_source_config() argument 201 flags, lisn, target, prio, sw_irq); in plpar_int_set_source_config() 206 target, prio, sw_irq); in plpar_int_set_source_config() 211 lisn, target, prio, rc); in plpar_int_set_source_config() 221 unsigned long *prio, in plpar_int_get_source_config() argument 231 target, prio, sw_irq); in plpar_int_get_source_config() 241 *prio = retbuf[1]; in plpar_int_get_source_config() 431 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) in xive_spapr_configure_irq() argument 436 prio, sw_irq); in xive_spapr_configure_irq() 441 static int xive_spapr_get_irq_config(u32 hw_irq, u32 *target, u8 *prio, in xive_spapr_get_irq_config() argument [all …]
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D | native.c | 100 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) in xive_native_configure_irq() argument 105 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq); in xive_native_configure_irq() 114 static int xive_native_get_irq_config(u32 hw_irq, u32 *target, u8 *prio, in xive_native_get_irq_config() argument 121 rc = opal_xive_get_irq_config(hw_irq, &vp, prio, &lirq); in xive_native_get_irq_config() 130 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, in xive_native_configure_queue() argument 151 rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL, in xive_native_configure_queue() 156 pr_err("Error %lld getting queue info prio %d\n", rc, prio); in xive_native_configure_queue() 173 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags); in xive_native_configure_queue() 179 pr_err("Error %lld setting queue for prio %d\n", rc, prio); in xive_native_configure_queue() 194 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) in __xive_native_disable_queue() argument [all …]
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D | xive-internal.h | 35 int (*configure_irq)(u32 hw_irq, u32 target, u8 prio, u32 sw_irq); 36 int (*get_irq_config)(u32 hw_irq, u32 *target, u8 *prio, 38 int (*setup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio); 39 void (*cleanup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
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D | common.c | 138 u8 prio = 0; in xive_scan_interrupts() local 144 prio = ffs(xc->pending_prio) - 1; in xive_scan_interrupts() 145 DBG_VERBOSE("scan_irq: trying prio %d\n", prio); in xive_scan_interrupts() 148 irq = xive_read_eq(&xc->queue[prio], just_peek); in xive_scan_interrupts() 166 xc->pending_prio &= ~(1 << prio); in xive_scan_interrupts() 173 q = &xc->queue[prio]; in xive_scan_interrupts() 185 prio = 0xff; in xive_scan_interrupts() 188 if (prio != xc->cppr) { in xive_scan_interrupts() 189 DBG_VERBOSE("scan_irq: adjusting CPPR to %d\n", prio); in xive_scan_interrupts() 190 xc->cppr = prio; in xive_scan_interrupts() [all …]
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/arch/c6x/kernel/ |
D | irq.c | 34 unsigned int prio = data->hwirq; in mask_core_irq() local 37 and_creg(IER, ~(1 << prio)); in mask_core_irq() 43 unsigned int prio = data->hwirq; in unmask_core_irq() local 46 or_creg(IER, 1 << prio); in unmask_core_irq() 58 asmlinkage void c6x_do_IRQ(unsigned int prio, struct pt_regs *regs) in c6x_do_IRQ() argument 64 generic_handle_irq(prio_to_virq[prio]); in c6x_do_IRQ()
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/arch/powerpc/kvm/ |
D | book3s_xive_template.c | 116 u8 prio = 0xff; in GLUE() local 128 prio = ffs(pending) - 1; in GLUE() 131 if (prio >= xc->cppr || prio > 7) { in GLUE() 133 prio = xc->mfrr; in GLUE() 140 q = &xc->queues[prio]; in GLUE() 173 if (hirq == XICS_IPI || (prio == 0 && !qpage)) { in GLUE() 194 pending &= ~(1 << prio); in GLUE() 216 if (prio >= xc->mfrr && xc->mfrr < xc->cppr) { in GLUE() 217 prio = xc->mfrr; in GLUE() 254 xc->cppr = prio; in GLUE() [all …]
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D | book3s_xive.c | 175 int kvmppc_xive_attach_escalation(struct kvm_vcpu *vcpu, u8 prio, in kvmppc_xive_attach_escalation() argument 179 struct xive_q *q = &xc->queues[prio]; in kvmppc_xive_attach_escalation() 184 if (xc->esc_virq[prio]) in kvmppc_xive_attach_escalation() 188 xc->esc_virq[prio] = irq_create_mapping(NULL, q->esc_irq); in kvmppc_xive_attach_escalation() 189 if (!xc->esc_virq[prio]) { in kvmppc_xive_attach_escalation() 191 prio, xc->server_num); in kvmppc_xive_attach_escalation() 200 vcpu->kvm->arch.lpid, xc->server_num, prio); in kvmppc_xive_attach_escalation() 203 prio, xc->server_num); in kvmppc_xive_attach_escalation() 208 pr_devel("Escalation %s irq %d (prio %d)\n", name, xc->esc_virq[prio], prio); in kvmppc_xive_attach_escalation() 210 rc = request_irq(xc->esc_virq[prio], xive_esc_irq, in kvmppc_xive_attach_escalation() [all …]
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D | book3s_xive.h | 244 static inline u8 xive_prio_from_guest(u8 prio) in xive_prio_from_guest() argument 246 if (prio == 0xff || prio < 6) in xive_prio_from_guest() 247 return prio; in xive_prio_from_guest() 251 static inline u8 xive_prio_to_guest(u8 prio) in xive_prio_to_guest() argument 253 return prio; in xive_prio_to_guest() 293 int kvmppc_xive_select_target(struct kvm *kvm, u32 *server, u8 prio); 294 int kvmppc_xive_attach_escalation(struct kvm_vcpu *vcpu, u8 prio,
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D | e500_emulate.c | 35 int prio = -1; in dbell2prio() local 39 prio = BOOKE_IRQPRIO_DBELL; in dbell2prio() 42 prio = BOOKE_IRQPRIO_DBELL_CRIT; in dbell2prio() 48 return prio; in dbell2prio() 54 int prio = dbell2prio(param); in kvmppc_e500_emul_msgclr() local 56 if (prio < 0) in kvmppc_e500_emul_msgclr() 59 clear_bit(prio, &vcpu->arch.pending_exceptions); in kvmppc_e500_emul_msgclr() 66 int prio = dbell2prio(rb); in kvmppc_e500_emul_msgsnd() local 71 if (prio < 0) in kvmppc_e500_emul_msgsnd() 77 set_bit(prio, &cvcpu->arch.pending_exceptions); in kvmppc_e500_emul_msgsnd()
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D | book3s_xive_native.c | 41 static void kvmppc_xive_native_cleanup_queue(struct kvm_vcpu *vcpu, int prio) in kvmppc_xive_native_cleanup_queue() argument 44 struct xive_q *q = &xc->queues[prio]; in kvmppc_xive_native_cleanup_queue() 46 xive_native_disable_queue(xc->vp_id, q, prio); in kvmppc_xive_native_cleanup_queue() 54 u8 prio, __be32 *qpage, in kvmppc_xive_native_configure_queue() argument 60 rc = xive_native_configure_queue(vp_id, q, prio, qpage, order, in kvmppc_xive_native_configure_queue() 809 unsigned int prio; in kvmppc_xive_reset() local 816 for (prio = 0; prio < KVMPPC_XIVE_Q_COUNT; prio++) { in kvmppc_xive_reset() 819 if (prio == 7 && xive->single_escalation) in kvmppc_xive_reset() 822 if (xc->esc_virq[prio]) { in kvmppc_xive_reset() 823 free_irq(xc->esc_virq[prio], vcpu); in kvmppc_xive_reset() [all …]
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D | book3s.c | 146 unsigned int prio; in kvmppc_book3s_vec2irqprio() local 149 case 0x100: prio = BOOK3S_IRQPRIO_SYSTEM_RESET; break; in kvmppc_book3s_vec2irqprio() 150 case 0x200: prio = BOOK3S_IRQPRIO_MACHINE_CHECK; break; in kvmppc_book3s_vec2irqprio() 151 case 0x300: prio = BOOK3S_IRQPRIO_DATA_STORAGE; break; in kvmppc_book3s_vec2irqprio() 152 case 0x380: prio = BOOK3S_IRQPRIO_DATA_SEGMENT; break; in kvmppc_book3s_vec2irqprio() 153 case 0x400: prio = BOOK3S_IRQPRIO_INST_STORAGE; break; in kvmppc_book3s_vec2irqprio() 154 case 0x480: prio = BOOK3S_IRQPRIO_INST_SEGMENT; break; in kvmppc_book3s_vec2irqprio() 155 case 0x500: prio = BOOK3S_IRQPRIO_EXTERNAL; break; in kvmppc_book3s_vec2irqprio() 156 case 0x600: prio = BOOK3S_IRQPRIO_ALIGNMENT; break; in kvmppc_book3s_vec2irqprio() 157 case 0x700: prio = BOOK3S_IRQPRIO_PROGRAM; break; in kvmppc_book3s_vec2irqprio() [all …]
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/arch/ia64/kernel/ |
D | sys_ia64.c | 73 long prio; in ia64_getpriority() local 75 prio = sys_getpriority(which, who); in ia64_getpriority() 76 if (prio >= 0) { in ia64_getpriority() 78 prio = 20 - prio; in ia64_getpriority() 80 return prio; in ia64_getpriority()
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/arch/powerpc/include/asm/ |
D | xive.h | 113 extern int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq); 115 extern int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, 117 extern void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio); 127 extern int xive_native_get_queue_info(u32 vp_id, uint32_t prio, 134 extern int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle, 136 extern int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle,
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/arch/unicore32/kernel/ |
D | dma.c | 24 puv3_dma_prio prio; member 32 int puv3_request_dma(char *name, puv3_dma_prio prio, in puv3_request_dma() argument 49 if ((dma_channels[i].prio == prio) && in puv3_request_dma() 56 } while (!found && prio--); in puv3_request_dma() 160 dma_channels[i].prio = min((i & 0x7) >> 1, DMA_PRIO_LOW); in puv3_init_dma()
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/arch/powerpc/boot/dts/ |
D | virtex440-ml507.dts | 72 xlnx,dcu-rd-ld-cache-plb-prio = <0>; 73 xlnx,dcu-rd-noncache-plb-prio = <0>; 74 xlnx,dcu-rd-touch-plb-prio = <0>; 75 xlnx,dcu-rd-urgent-plb-prio = <0>; 76 xlnx,dcu-wr-flush-plb-prio = <0>; 77 xlnx,dcu-wr-store-plb-prio = <0>; 78 xlnx,dcu-wr-urgent-plb-prio = <0>; 80 xlnx,dma0-plb-prio = <0>; 86 xlnx,dma1-plb-prio = <0>; 92 xlnx,dma2-plb-prio = <0>; [all …]
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D | virtex440-ml510.dts | 68 xlnx,dcu-rd-ld-cache-plb-prio = <0x0>; 69 xlnx,dcu-rd-noncache-plb-prio = <0x0>; 70 xlnx,dcu-rd-touch-plb-prio = <0x0>; 71 xlnx,dcu-rd-urgent-plb-prio = <0x0>; 72 xlnx,dcu-wr-flush-plb-prio = <0x0>; 73 xlnx,dcu-wr-store-plb-prio = <0x0>; 74 xlnx,dcu-wr-urgent-plb-prio = <0x0>; 76 xlnx,dma0-plb-prio = <0x0>; 82 xlnx,dma1-plb-prio = <0x0>; 88 xlnx,dma2-plb-prio = <0x0>; [all …]
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/arch/powerpc/platforms/cell/spufs/ |
D | sched.c | 74 #define SCALE_PRIO(x, prio) \ argument 75 max(x * (MAX_PRIO - prio) / (MAX_USER_PRIO / 2), MIN_SPU_TIMESLICE) 87 if (ctx->prio < NORMAL_PRIO) in spu_set_timeslice() 88 ctx->time_slice = SCALE_PRIO(DEF_SPU_TIMESLICE * 4, ctx->prio); in spu_set_timeslice() 90 ctx->time_slice = SCALE_PRIO(DEF_SPU_TIMESLICE, ctx->prio); in spu_set_timeslice() 117 if (rt_prio(current->prio)) in __spu_update_sched_info() 118 ctx->prio = current->prio; in __spu_update_sched_info() 120 ctx->prio = current->static_prio; in __spu_update_sched_info() 497 list_add_tail(&ctx->rq, &spu_prio->runq[ctx->prio]); in __spu_add_to_rq() 498 set_bit(ctx->prio, spu_prio->bitmap); in __spu_add_to_rq() [all …]
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/arch/arc/kernel/ |
D | intc-arcv2.c | 17 unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8; member 19 unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3; 67 irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */ in arc_init_IRQ()
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/arch/x86/kernel/ |
D | itmt.c | 190 void sched_set_itmt_core_prio(int prio, int core_cpu) in sched_set_itmt_core_prio() argument 202 smt_prio = prio * smp_num_siblings / i; in sched_set_itmt_core_prio()
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/arch/powerpc/platforms/cell/ |
D | interrupt.c | 57 return IIC_IRQ_TYPE_IPI | (bits.prio >> 4); in iic_pending_to_hwnum() 73 out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]); in iic_eoi() 147 iic->eoi_stack[++iic->eoi_ptr] = pending.prio; in iic_get_irq() 154 out_be64(&this_cpu_ptr(&cpu_iic)->regs->prio, 0xff); in iic_setup_cpu() 291 out_be64(&iic->regs->prio, 0); in init_one_iic()
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/arch/x86/include/asm/ |
D | topology.h | 173 void sched_set_itmt_core_prio(int prio, int core_cpu); 184 static inline void sched_set_itmt_core_prio(int prio, int core_cpu) in sched_set_itmt_core_prio() argument
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/arch/c6x/include/asm/ |
D | irq.h | 46 extern asmlinkage void c6x_do_IRQ(unsigned int prio, struct pt_regs *regs);
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/arch/unicore32/include/mach/ |
D | dma.h | 28 puv3_dma_prio prio,
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