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/arch/openrisc/lib/
Dmemset.S44 l.or r17, r5, r0 // Set r17 = n
56 l.addi r17, r17, -1 // Decrease n
64 l.addi r17, r17, -1 // Decrease n
72 l.addi r17, r17, -1 // Decrease n
77 l.addi r17, r17, -4 // Decrease n
78 l.sfgeui r17, 4
83 l.sfeqi r17, 0
87 3: l.addi r17, r17, -1 // Decrease n
89 l.sfnei r17, 0
/arch/ia64/kernel/
Divt.S124 shr.u r17=r16,61 // get the region number into r17
137 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
140 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
149 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
150 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
158 ld8 r17=[r17] // get *pgd (may be 0)
160 (p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?
162 dep r28=r28,r17,3,(PAGE_SHIFT-3) // r28=pud_offset(pgd,addr)
168 dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
170 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr)
[all …]
Dminstate.h61 ld1 r17=[r16]; /* load current->thread.on_ustack flag */ \
68 cmp.eq pKStk,pUStk=r0,r17; /* are we in kernel mode already? */ \
85 adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \
88 lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \
91 lfetch.fault.excl.nt1 [r17]; \
97 adds r17=PT(R9),r1; /* initialize second base pointer */ \
101 .mem.offset 8,0; st8.spill [r17]=r9,16; \
104 .mem.offset 8,0; st8.spill [r17]=r11,24; \
107 st8 [r17]=r30,16; /* save cr.ifs */ \
115 st8 [r17]=r26,16; /* save ar.pfs */ \
[all …]
Dgate.S124 ld8 r17=[base0],(ARG0_OFF-SIGHANDLER_OFF) // get pointer to signal handler's plabel
138 ld8 r10=[r17],8 // get signal handler entry point
141 ld8 gp=[r17] // get signal handler's global pointer
249 ld8 r17=[r16]
253 mov ar.rsc=r17 // put RSE into enforced lazy mode
254 shr.u r17=r17,16
256 sub r14=r14,r17 // r14 (bspstore1) <- bsp1 - (sc_loadrs >> 16)
257 shr.u r17=r17,3 // r17 <- (sc_loadrs >> 19)
262 add r14=r14,r17 // r14 <- rse_slot_num(bspstore1) + (sc_loadrs >> 19)
266 sub r14=r14,r17 // r14 <- -rse_num_regs(bspstore1, bsp1)
[all …]
Dfsys.S65 add r17=IA64_TASK_SIGNAL_OFFSET,r16
67 ld8 r17=[r17] // r17 = current->signal
71 add r17=IA64_SIGNAL_PIDS_TGID_OFFSET,r17
74 ld8 r17=[r17] // r17 = current->signal->pids[PIDTYPE_TGID]
76 add r8=IA64_PID_LEVEL_OFFSET,r17
79 add r17=IA64_PID_UPID_OFFSET,r17 // r17 = &pid->numbers[0]
83 add r17=r17,r8 // r17 = &pid->numbers[pid->level]
85 ld4 r8=[r17] // r8 = pid->numbers[pid->level].nr
87 mov r17=0
99 add r17=IA64_TASK_THREAD_PID_OFFSET,r16
[all …]
Dhead.S240 movl r17=KERNEL_START
243 mov cr.ifa=r17
267 movl r17=1f
269 mov cr.iip=r17
279 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)
321 movl r17=PAGE_KERNEL
326 or r18=r17,r18
329 mov r17=rr[r2]
332 dep r17=0,r17,8,24
334 mov cr.itir=r17
[all …]
Dentry.S246 .save @priunat,r17
247 mov r17=ar.unat // preserve caller's
347 st8 [r14]=r17,SW(AR_FPSR)-SW(CALLER_UNAT) // save caller_unat
390 ld8 r17=[r3],(SW(AR_RNAT)-SW(AR_LC)) // ar.lc
443 mov ar.lc=r17
472 adds r17=PT(F7)+16,sp
475 stf.spill [r17]=f7,32
478 stf.spill [r17]=f9,32
481 stf.spill [r17]=f11
489 adds r17=PT(F7)+16,sp
[all …]
Dmca_asm.S65 addl r17=O(PTCE_STRIDE),r2
70 ld4 r21=[r17],4 // r21=ptce_stride[0]
73 ld4 r22=[r17] // r22=ptce_stride[1]
170 movl r17=KERNEL_START
173 mov cr.ifa=r17
178 dep r17=0,r19,0, KERNEL_TR_PAGE_SHIFT
180 or r18=r17,r18
316 mov r22=r17 // *minstate
485 st8 [temp1]=r17,16 // pal_min_state
626 add r1=32*1,r17
[all …]
Drelocate_kernel.S64 addl r17=O(PTCE_STRIDE),r2
69 ld4 r21=[r17],4 // r21=ptce_stride[0]
72 ld4 r22=[r17] // r22=ptce_stride[1]
137 (p6) and r17=r30, r16
157 st8 [r17]=r14;;
158 fc.i r17
159 add r17=8, r17
264 st8 [in0]=r17, 8 // r17
Desi_stub.S78 movl r17=PSR_BITS_TO_SET
80 or loc3=loc3,r17
Defi_stub.S60 movl r17=PSR_BITS_TO_SET
62 or loc3=loc3,r17
Dpal.S175 movl r17=PAL_PSR_BITS_TO_SET
177 or loc3=loc3,r17 // add in psr the bits to set
227 movl r17=PAL_PSR_BITS_TO_SET
229 or loc3=loc3,r17 // add in psr the bits to set
/arch/unicore32/lib/
Dcopy_page.S24 stm.w (r17 - r19, lr), [sp-]
25 mov r17, r0
31 stm.w (r0 - r15), [r17]+
35 ldm.w (r17 - r19, pc), [sp]+
/arch/ia64/lib/
Dxor.S28 mov r17 = in2
37 (p[0]) ld8.nta s2[0] = [r17], 8
66 mov r17 = in2
76 (p[0]) ld8.nta s2[0] = [r17], 8
107 mov r17 = in2
118 (p[0]) ld8.nta s2[0] = [r17], 8
151 mov r17 = in2
163 (p[0]) ld8.nta s2[0] = [r17], 8
/arch/nds32/kernel/
Dex-entry.S55 movi $r17, -1
72 slti $r17, $r16, #4
73 bnez $r17, 1f
74 addi $r17, $r19, #-2
75 mtsr $r17, $PSW
Dex-scall.S44 addi $r17, $r13, #4 ! $r13 is $IPC
45 swi $r17, [$sp + IPC_OFFSET]
/arch/powerpc/lib/
Dcopypage_power7.S104 std r17,STK_REG(R17)(r1)
121 ld r17,96(r4)
138 std r17,96(r3)
148 ld r17,STK_REG(R17)(r1)
Dmemcpy_mcsafe_64.S31 ld r17,STK_REG(R17)(r1)
93 std r17,STK_REG(R17)(r1)
118 err2; ld r17,80(r4)
135 err2; std r17,80(r3)
175 ld r17,STK_REG(R17)(r1)
/arch/powerpc/kernel/
Didle_book3s.S58 std r17,-8*4(r1)
103 ld r17,-8*4(r1)
160 std r17,-8*4(r1)
/arch/nios2/kernel/
Dinsnemu.S132 stw r17, 68(sp)
257 movi r17, 0
269 xor r17, r3, r5 /* MSB contains sign of quotient */
340 bge r17, zero, quotient_is_nonnegative
563 ldw r17, 68(sp)
/arch/powerpc/purgatory/
Dtrampoline.S43 mr %r17,%r3 /* save cpu id to r17 */
62 STWX_BE %r17,%r3,%r4 /* Store my cpu as __be32 at byte 28 */
/arch/csky/abiv2/inc/abi/
Dswitch_context.h25 unsigned long r17; member
/arch/nds32/lib/
Dcopy_template.S44 lmw1 $r17, $r1, $r24
46 smw1 $r17, $r0, $r24
/arch/arc/include/asm/
Dunwind.h31 unsigned long r17; member
90 PTREGS_INFO(r17), \
/arch/alpha/include/uapi/asm/
Dptrace.h50 unsigned long r17; member

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