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/arch/arm/include/debug/
Dsamsung.S12 .macro fifo_level_s5pv210 rd, rx
13 ldr \rd, [\rx, # S3C2410_UFSTAT]
14 ARM_BE8(rev \rd, \rd)
15 and \rd, \rd, #S5PV210_UFSTAT_TXMASK
18 .macro fifo_full_s5pv210 rd, rx
19 ldr \rd, [\rx, # S3C2410_UFSTAT]
20 ARM_BE8(rev \rd, \rd)
21 tst \rd, #S5PV210_UFSTAT_TXFULL
27 .macro fifo_level_s3c2440 rd, rx
28 ldr \rd, [\rx, # S3C2410_UFSTAT]
[all …]
D8250.S15 .macro store, rd, rx:vararg
16 ARM_BE8(rev \rd, \rd)
17 str \rd, \rx
18 ARM_BE8(rev \rd, \rd)
21 .macro load, rd, rx:vararg
22 ldr \rd, \rx
23 ARM_BE8(rev \rd, \rd)
26 .macro store, rd, rx:vararg
27 strb \rd, \rx
30 .macro load, rd, rx:vararg
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Dmsm.S14 .macro senduart, rd, rx
15 ARM_BE8(rev \rd, \rd )
17 str \rd, [\rx, #0x70]
20 .macro waituart, rd, rx
22 ldr \rd, [\rx, #0x08]
23 ARM_BE8(rev \rd, \rd )
24 tst \rd, #0x08
27 1001: ldr \rd, [\rx, #0x14]
28 ARM_BE8(rev \rd, \rd )
29 tst \rd, #0x80
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Dicedcc.S15 .macro senduart, rd, rx
16 mcr p14, 0, \rd, c0, c5, 0
19 .macro busyuart, rd, rx
26 .macro waituart, rd, rx
27 mov \rd, #0x2000000
29 subs \rd, \rd, #1
39 .macro senduart, rd, rx
40 mcr p14, 0, \rd, c8, c0, 0
43 .macro busyuart, rd, rx
50 .macro waituart, rd, rx
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Dpl01x.S25 .macro senduart,rd,rx
26 strb \rd, [\rx, #UART01x_DR]
29 .macro waituart,rd,rx
30 1001: ldr \rd, [\rx, #UART01x_FR]
31 ARM_BE8( rev \rd, \rd )
32 tst \rd, #UART01x_FR_TXFF
36 .macro busyuart,rd,rx
37 1001: ldr \rd, [\rx, #UART01x_FR]
38 ARM_BE8( rev \rd, \rd )
39 tst \rd, #UART01x_FR_BUSY
Drenesas-scif.S36 .macro waituart, rd, rx
37 1001: ldrh \rd, [\rx, #FSR]
38 tst \rd, #TDFE
42 .macro senduart, rd, rx
43 strb \rd, [\rx, #FTDR]
44 ldrh \rd, [\rx, #FSR]
45 bic \rd, \rd, #TEND
46 strh \rd, [\rx, #FSR]
49 .macro busyuart, rd, rx
50 1001: ldrh \rd, [\rx, #FSR]
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Dzynq.S32 .macro senduart,rd,rx
33 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
36 .macro waituart,rd,rx
37 1001: ldr \rd, [\rx, #UART_SR_OFFSET]
38 ARM_BE8( rev \rd, \rd )
39 tst \rd, #UART_SR_TXEMPTY
43 .macro busyuart,rd,rx
44 1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
45 ARM_BE8( rev \rd, \rd )
46 tst \rd, #UART_SR_TXFULL @
Dimx.S33 .macro senduart,rd,rx
34 ARM_BE8(rev \rd, \rd)
35 str \rd, [\rx, #0x40] @ TXDATA
38 .macro waituart,rd,rx
41 .macro busyuart,rd,rx
42 1002: ldr \rd, [\rx, #0x98] @ SR2
43 ARM_BE8(rev \rd, \rd)
44 tst \rd, #1 << 3 @ TXDC
Domap2plus.S63 .macro senduart,rd,rx
64 orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
66 strb \rd, [\rx] @ send lower byte of rd
67 orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
68 bic \rd, \rd, #(0xff << 24) @ restore original rd
71 .macro busyuart,rd,rx
72 1001: ldrb \rd, [\rx] @ rx contains UART_LSR address
73 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
74 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
78 .macro waituart,rd,rx
Dbcm63xx.S15 .macro senduart, rd, rx
17 strb \rd, [\rx, #UART_FIFO_REG]
20 .macro waituart, rd, rx
21 1001: ldr \rd, [\rx, #UART_IR_REG]
22 tst \rd, #(1 << UART_IR_TXEMPTY)
26 .macro busyuart, rd, rx
27 1002: ldr \rd, [\rx, #UART_IR_REG]
28 tst \rd, #(1 << UART_IR_TXTRESH)
Dmeson.S18 .macro senduart,rd,rx
19 str \rd, [\rx, #MESON_AO_UART_WFIFO]
22 .macro busyuart,rd,rx
23 1002: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
24 tst \rd, #MESON_AO_UART_TX_FIFO_EMPTY
28 .macro waituart,rd,rx
29 1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
30 tst \rd, #MESON_AO_UART_TX_FIFO_FULL
Defm32.S28 .macro senduart,rd,rx
29 strb \rd, [\rx, #UARTn_TXDATA]
32 .macro waituart,rd,rx
33 1001: ldr \rd, [\rx, #UARTn_STATUS]
34 tst \rd, #UARTn_STATUS_TXBL
38 .macro busyuart,rd,rx
39 1001: ldr \rd, [\rx, UARTn_STATUS]
40 tst \rd, #UARTn_STATUS_TXC
Ds3c24xx.S21 .macro fifo_full_s3c2410 rd, rx
22 ldr \rd, [\rx, # S3C2410_UFSTAT]
23 tst \rd, #S3C2410_UFSTAT_TXFULL
26 .macro fifo_level_s3c2410 rd, rx
27 ldr \rd, [\rx, # S3C2410_UFSTAT]
28 and \rd, \rd, #S3C2410_UFSTAT_TXMASK
Dvt8500.S21 .macro senduart,rd,rx
22 strb \rd, [\rx, #0]
25 .macro busyuart,rd,rx
26 1001: ldr \rd, [\rx, #0x1c]
27 ands \rd, \rd, #0x2
31 .macro waituart,rd,rx
Dstm32.S27 .macro senduart,rd,rx
28 strb \rd, [\rx, #STM32_USART_TDR_OFF]
31 .macro waituart,rd,rx
32 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
33 tst \rd, #STM32_USART_TXE @ TXE = 1 = tx empty
37 .macro busyuart,rd,rx
38 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
39 tst \rd, #STM32_USART_TC @ TC = 1 = tx complete
Dsti.S44 .macro senduart,rd,rx
45 strb \rd, [\rx, #ASC_TX_BUF_OFF]
48 .macro waituart,rd,rx
49 1001: ldr \rd, [\rx, #ASC_STA_OFF]
50 tst \rd, #ASC_STA_TX_FULL
54 .macro busyuart,rd,rx
55 1001: ldr \rd, [\rx, #ASC_STA_OFF]
56 tst \rd, #ASC_STA_TX_EMPTY
Dat91.S18 .macro senduart,rd,rx
19 strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
22 .macro waituart,rd,rx
23 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
24 tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
28 .macro busyuart,rd,rx
29 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
30 tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
/arch/arm/net/
Dbpf_jit_32.h159 #define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm)) argument
161 #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) argument
165 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) argument
166 #define ARM_ADDS_R(rd, rn, rm) _AL3_R(ARM_INST_ADDS, rd, rn, rm) argument
167 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) argument
168 #define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm) argument
169 #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm) argument
170 #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm) argument
172 #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) argument
173 #define ARM_ANDS_R(rd, rn, rm) _AL3_R(ARM_INST_ANDS, rd, rn, rm) argument
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Dbpf_jit_32.c414 static inline void emit_mov_i_no8m(const u8 rd, u32 val, struct jit_ctx *ctx) in emit_mov_i_no8m() argument
417 emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx); in emit_mov_i_no8m()
419 emit(ARM_MOVW(rd, val & 0xffff), ctx); in emit_mov_i_no8m()
421 emit(ARM_MOVT(rd, val >> 16), ctx); in emit_mov_i_no8m()
425 static inline void emit_mov_i(const u8 rd, u32 val, struct jit_ctx *ctx) in emit_mov_i() argument
430 emit(ARM_MOV_I(rd, imm12), ctx); in emit_mov_i()
432 emit_mov_i_no8m(rd, val, ctx); in emit_mov_i()
465 static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op) in emit_udivmod() argument
472 emit(ARM_UDIV(rd, rm, rn), ctx); in emit_udivmod()
475 emit(ARM_MLS(rd, rn, ARM_IP, rm), ctx); in emit_udivmod()
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/arch/riscv/net/
Dbpf_jit_comp.c162 static u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, u8 opcode) in rv_r_insn() argument
165 (rd << 7) | opcode; in rv_r_insn()
168 static u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode) in rv_i_insn() argument
170 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) | in rv_i_insn()
191 static u32 rv_u_insn(u32 imm31_12, u8 rd, u8 opcode) in rv_u_insn() argument
193 return (imm31_12 << 12) | (rd << 7) | opcode; in rv_u_insn()
196 static u32 rv_uj_insn(u32 imm20_1, u8 rd, u8 opcode) in rv_uj_insn() argument
203 return (imm << 12) | (rd << 7) | opcode; in rv_uj_insn()
207 u8 funct3, u8 rd, u8 opcode) in rv_amo_insn() argument
211 return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode); in rv_amo_insn()
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/arch/sparc/include/asm/
Dhead_32.h13 rd %psr, %l0; b label; rd %wim, %l3; nop;
16 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
17 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
21 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
38 rd %psr, %l0;
42 rd %psr,%l0; \
50 rd %psr,%l0; \
59 b getcc_trap_handler; rd %psr, %l0; nop; nop;
63 b setcc_trap_handler; rd %psr, %l0; nop; nop;
67 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
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/arch/arm/mach-tegra/
Dsleep.h51 .macro cpu_to_halt_reg rd, rcpu
53 subne \rd, \rcpu, #1
54 movne \rd, \rd, lsl #3
55 addne \rd, \rd, #0x14
56 moveq \rd, #0
60 .macro cpu_to_csr_reg rd, rcpu
62 subne \rd, \rcpu, #1
63 movne \rd, \rd, lsl #3
64 addne \rd, \rd, #0x18
65 moveq \rd, #8
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/arch/unicore32/mm/
Dproc-macros.S38 .macro vma_vm_mm, rd, rn
39 ldw \rd, [\rn+], #VMA_VM_MM
45 .macro vma_vm_flags, rd, rn
46 ldw \rd, [\rn+], #VMA_VM_FLAGS
49 .macro tsk_mm, rd, rn
50 ldw \rd, [\rn+], #TI_TASK
51 ldw \rd, [\rd+], #TSK_ACTIVE_MM
57 .macro act_mm, rd argument
58 andn \rd, sp, #8128
59 andn \rd, \rd, #63
[all …]
/arch/unicore32/kernel/
Ddebug-macro.S14 .macro put_word_ocd, rd, rx=r16
18 movc p1.c1, \rd, #1
26 .macro senduart, rd, rx
27 put_word_ocd \rd, \rx
30 .macro busyuart, rd, rx
33 .macro waituart, rd, rx
70 .macro senduart,rd,rx
71 str \rd, [\rx, #UART_THR_OFFSET]
74 .macro waituart,rd,rx
75 1001: ldr \rd, [\rx, #UART_LSR_OFFSET]
[all …]
/arch/arm/lib/
Dio-writesb.S10 .macro outword, rd argument
12 strb \rd, [r0]
13 mov \rd, \rd, lsr #8
14 strb \rd, [r0]
15 mov \rd, \rd, lsr #8
16 strb \rd, [r0]
17 mov \rd, \rd, lsr #8
18 strb \rd, [r0]
20 mov lr, \rd, lsr #24
22 mov lr, \rd, lsr #16
[all …]

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