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Searched refs:rn (Results 1 – 25 of 36) sorted by relevance

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/arch/arm/net/
Dbpf_jit_32.h159 #define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm)) argument
161 #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) argument
165 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) argument
166 #define ARM_ADDS_R(rd, rn, rm) _AL3_R(ARM_INST_ADDS, rd, rn, rm) argument
167 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) argument
168 #define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm) argument
169 #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm) argument
170 #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm) argument
172 #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) argument
173 #define ARM_ANDS_R(rd, rn, rm) _AL3_R(ARM_INST_ANDS, rd, rn, rm) argument
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Dbpf_jit_32.c299 static u32 arm_bpf_ldst_imm12(u32 op, u8 rt, u8 rn, s16 imm12) in arm_bpf_ldst_imm12() argument
301 op |= rt << 12 | rn << 16; in arm_bpf_ldst_imm12()
309 static u32 arm_bpf_ldst_imm8(u32 op, u8 rt, u8 rn, s16 imm8) in arm_bpf_ldst_imm8() argument
311 op |= rt << 12 | rn << 16; in arm_bpf_ldst_imm8()
319 #define ARM_LDR_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_LDR_I, rt, rn, off) argument
320 #define ARM_LDRB_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_LDRB_I, rt, rn, off) argument
321 #define ARM_LDRD_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRD_I, rt, rn, off) argument
322 #define ARM_LDRH_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRH_I, rt, rn, off) argument
324 #define ARM_STR_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_STR_I, rt, rn, off) argument
325 #define ARM_STRB_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_STRB_I, rt, rn, off) argument
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/arch/powerpc/include/asm/
Ddcr-native.h53 #define mfdcr(rn) \ argument
55 if (__builtin_constant_p(rn) && rn < 1024) \
56 asm volatile("mfdcr %0," __stringify(rn) \
59 rval = mfdcrx(rn); \
61 rval = __mfdcr(rn); \
64 #define mtdcr(rn, v) \ argument
66 if (__builtin_constant_p(rn) && rn < 1024) \
67 asm volatile("mtdcr " __stringify(rn) ",%0" \
70 mtdcrx(rn, v); \
72 __mtdcr(rn, v); \
Dreg_fsl_emb.h14 #define mfpmr(rn) ({unsigned int rval; \ argument
15 asm volatile("mfpmr %0," __stringify(rn) \
17 #define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v)) argument
/arch/arm/probes/kprobes/
Dactions-arm.c74 int rn = (insn >> 16) & 0xf; in emulate_ldrdstrd() local
79 register unsigned long rnv asm("r2") = (rn == 15) ? pc in emulate_ldrdstrd()
80 : regs->uregs[rn]; in emulate_ldrdstrd()
94 regs->uregs[rn] = rnv; in emulate_ldrdstrd()
103 int rn = (insn >> 16) & 0xf; in emulate_ldr() local
107 register unsigned long rnv asm("r2") = (rn == 15) ? pc in emulate_ldr()
108 : regs->uregs[rn]; in emulate_ldr()
124 regs->uregs[rn] = rnv; in emulate_ldr()
134 int rn = (insn >> 16) & 0xf; in emulate_str() local
139 register unsigned long rnv asm("r2") = (rn == 15) ? rnpc in emulate_str()
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Dactions-common.c22 int rn = (insn >> 16) & 0xf; in simulate_ldm1stm1() local
27 long *addr = (long *)regs->uregs[rn]; in simulate_ldm1stm1()
56 regs->uregs[rn] = (long)addr; in simulate_ldm1stm1()
131 int rn = (insn >> 16) & 0xf; in kprobe_decode_ldmstm() local
133 if (rn <= 12 && (reglist & 0xe000) == 0) { in kprobe_decode_ldmstm()
137 } else if (rn >= 2 && (reglist & 0x8003) == 0) { in kprobe_decode_ldmstm()
139 rn -= 2; in kprobe_decode_ldmstm()
143 } else if (rn >= 3 && (reglist & 0x0007) == 0) { in kprobe_decode_ldmstm()
146 rn -= 3; in kprobe_decode_ldmstm()
155 (rn << 16) | reglist); in kprobe_decode_ldmstm()
Dactions-thumb.c28 int rn = (insn >> 16) & 0xf; in t32_simulate_table_branch() local
31 unsigned long rnv = (rn == 15) ? pc : regs->uregs[rn]; in t32_simulate_table_branch()
164 int rn = (insn >> 16) & 0xf; in t32_emulate_ldrdstrd() local
168 register unsigned long rnv asm("r2") = (rn == 15) ? pc in t32_emulate_ldrdstrd()
169 : regs->uregs[rn]; in t32_emulate_ldrdstrd()
178 if (rn != 15) in t32_emulate_ldrdstrd()
179 regs->uregs[rn] = rnv; /* Writeback base register */ in t32_emulate_ldrdstrd()
189 int rn = (insn >> 16) & 0xf; in t32_emulate_ldrstr() local
193 register unsigned long rnv asm("r2") = regs->uregs[rn]; in t32_emulate_ldrstr()
203 regs->uregs[rn] = rnv; /* Writeback base register */ in t32_emulate_ldrstr()
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Dcheckers-arm.c122 unsigned int rn = (insn >> 16) & 0xf; in arm_check_regs_ldmstm() local
123 asi->register_usage_flags = reglist | (1 << rn); in arm_check_regs_ldmstm()
/arch/arm64/kvm/
Dva_layout.c64 static u32 compute_instruction(int n, u32 rd, u32 rn) in compute_instruction() argument
72 rn, rd, va_mask); in compute_instruction()
78 rn, rn, rd, in compute_instruction()
83 insn = aarch64_insn_gen_add_sub_imm(rd, rn, in compute_instruction()
90 insn = aarch64_insn_gen_add_sub_imm(rd, rn, in compute_instruction()
99 rn, rn, rd, 64 - tag_lsb); in compute_instruction()
117 u32 rd, rn, insn, oinsn; in kvm_update_va_mask() local
134 rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, oinsn); in kvm_update_va_mask()
136 insn = compute_instruction(i, rd, rn); in kvm_update_va_mask()
/arch/powerpc/boot/
Dreg.h18 #define mfspr(rn) ({unsigned long rval; \ argument
19 asm volatile("mfspr %0," __stringify(rn) \
21 #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)) argument
Ddcr.h5 #define mfdcr(rn) \ argument
8 asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
11 #define mtdcr(rn, val) \ argument
12 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
13 #define mfdcrx(rn) \ argument
16 asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
19 #define mtdcrx(rn, val) \ argument
21 asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
/arch/unicore32/mm/
Dproc-macros.S38 .macro vma_vm_mm, rd, rn argument
39 ldw \rd, [\rn+], #VMA_VM_MM
45 .macro vma_vm_flags, rd, rn argument
46 ldw \rd, [\rn+], #VMA_VM_FLAGS
49 .macro tsk_mm, rd, rn argument
50 ldw \rd, [\rn+], #TI_TASK
67 .macro mmid, rd, rn argument
68 ldw \rd, [\rn+], #MM_CONTEXT_ID
74 .macro asid, rd, rn argument
75 and \rd, \rn, #255
Dalignment.c289 unsigned int rd, rn, pc_correction, reg_correction, nr_regs, regbits; in do_alignment_ldmstm() local
300 rn = RN_BITS(instr); in do_alignment_ldmstm()
301 newaddr = eaddr = regs->uregs[rn]; in do_alignment_ldmstm()
341 regs->uregs[rn] = newaddr; in do_alignment_ldmstm()
/arch/arm64/crypto/
Dsm3-ce-core.S15 .macro sm3partw1, rd, rn, rm
16 .inst 0xce60c000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
19 .macro sm3partw2, rd, rn, rm
20 .inst 0xce60c400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
23 .macro sm3ss1, rd, rn, rm, ra
24 .inst 0xce400000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
27 .macro sm3tt1a, rd, rn, rm, imm2
28 .inst 0xce408000 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
31 .macro sm3tt1b, rd, rn, rm, imm2
32 .inst 0xce408400 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
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Dsha512-ce-core.S20 .macro sha512h, rd, rn, rm
21 .inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
24 .macro sha512h2, rd, rn, rm
25 .inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
28 .macro sha512su0, rd, rn argument
29 .inst 0xcec08000 | .L\rd | (.L\rn << 5)
32 .macro sha512su1, rd, rn, rm
33 .inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
Dsm4-ce-core.S10 .macro sm4e, rd, rn argument
11 .inst 0xcec08400 | .L\rd | (.L\rn << 5)
Dsha3-ce-core.S23 .macro eor3, rd, rn, rm, ra
24 .inst 0xce000000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
27 .macro rax1, rd, rn, rm
28 .inst 0xce608c00 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
31 .macro bcax, rd, rn, rm, ra
32 .inst 0xce200000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
35 .macro xar, rd, rn, rm, imm6
36 .inst 0xce800000 | .L\rd | (.L\rn << 5) | ((\imm6) << 10) | (.L\rm << 16)
/arch/sh/kernel/
Dtraps_32.c89 unsigned long *rm, *rn; in handle_unaligned_ins() local
94 rn = &regs->regs[index]; in handle_unaligned_ins()
115 dst = (unsigned char *)rn; in handle_unaligned_ins()
131 dstu = (unsigned char __user *)*rn; in handle_unaligned_ins()
142 dstu = (unsigned char __user *)*rn; in handle_unaligned_ins()
152 *rn -= count; in handle_unaligned_ins()
154 dstu = (unsigned char __user *)*rn; in handle_unaligned_ins()
166 dst = (unsigned char *)rn; in handle_unaligned_ins()
178 dst = (unsigned char*) rn; in handle_unaligned_ins()
226 dst = (unsigned char *)rn; in handle_unaligned_ins()
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Ddisassemble.c301 int rn = 0; in print_sh_insn() local
361 rn = nibs[n]; in print_sh_insn()
367 rn = (nibs[n] & 0xc) >> 2; in print_sh_insn()
393 printk("r%d", rn); in print_sh_insn()
396 printk("@r%d+", rn); in print_sh_insn()
399 printk("@-r%d", rn); in print_sh_insn()
402 printk("@r%d", rn); in print_sh_insn()
405 printk("@(%d,r%d)", imm, rn); in print_sh_insn()
432 printk("@(r0,r%d)", rn); in print_sh_insn()
479 printk("fr%d", rn); in print_sh_insn()
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/arch/arm/mm/
Dabort-lv4t.S37 /* 0 */ b .data_arm_lateldrhpost @ ldrh rd, [rn], #m/rm
38 /* 1 */ b .data_arm_lateldrhpre @ ldrh rd, [rn, #m/rm]
41 /* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
42 /* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
43 /* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
44 /* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
45 /* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
46 /* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
49 /* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
50 /* d */ b do_DataAbort @ ldc rd, [rn, #m]
Dproc-macros.S18 .macro vma_vm_mm, rd, rn argument
19 ldr \rd, [\rn, #VMA_VM_MM]
25 .macro vma_vm_flags, rd, rn argument
26 ldr \rd, [\rn, #VMA_VM_FLAGS]
46 .macro mmid, rd, rn argument
48 ldr \rd, [\rn, #MM_CONTEXT_ID + 4 ]
50 ldr \rd, [\rn, #MM_CONTEXT_ID]
57 .macro asid, rd, rn argument
58 and \rd, \rn, #255
/arch/arm/mach-tegra/
Dsleep.h43 .macro wait_until, rn, base, tmp
44 add \rn, \rn, #1
46 cmp \tmp, \rn
/arch/arm/probes/uprobes/
Dactions-arm.c166 int rn = (insn >> 16) & 0xf; in uprobe_decode_ldmstm() local
168 unsigned used = reglist | (1 << rn); in uprobe_decode_ldmstm()
170 if (rn == 15) in uprobe_decode_ldmstm()
/arch/arm64/kernel/
Dentry-ftrace.S56 .macro mcount_adjust_addr rd, rn argument
57 sub \rd, \rn, #AARCH64_INSN_SIZE
/arch/powerpc/lib/
Dsstep.c37 extern void get_fpr(int rn, double *p);
38 extern void put_fpr(int rn, const double *p);
39 extern void get_vr(int rn, __vector128 *p);
40 extern void put_vr(int rn, __vector128 *p);
461 int err, rn, nb; in do_fp_load() local
474 rn = op->reg; in do_fp_load()
493 put_fpr(rn, &u.d[0]); in do_fp_load()
495 current->thread.TS_FPR(rn) = u.l[0]; in do_fp_load()
498 rn |= 1; in do_fp_load()
500 put_fpr(rn, &u.d[1]); in do_fp_load()
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