/drivers/gpu/drm/amd/amdgpu/ |
D | gfx_v6_0.c | 503 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init() 530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init() 537 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init() 548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init() 556 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init() 697 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init() 745 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init() 777 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init() 785 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init() 794 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init() [all …]
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D | gfx_v8_0.c | 2267 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init() 2271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init() 2295 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init() 2299 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init() 2459 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init() 2463 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init() 2479 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init() 2487 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init() 2491 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init() 2648 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init() [all …]
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D | gfx_v7_0.c | 1167 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init() 1171 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init() 1175 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init() 1179 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init() 1183 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init() 1203 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init() 1207 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init() 1211 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init() 1350 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init() 1354 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init() [all …]
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D | sid.h | 1210 # define ADDR_SURF_BANK_HEIGHT_1 0 macro
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/drivers/gpu/drm/radeon/ |
D | cik.c | 2458 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init() 2462 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init() 2466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init() 2470 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init() 2474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init() 2486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init() 2490 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init() 2494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init() 2498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init() 2502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init() [all …]
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D | si.c | 2580 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init() 2634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init() 2670 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init() 2679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init() 2715 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init() 2724 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init() 2795 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init() 2849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init() 2885 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init() 2894 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init() [all …]
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D | sid.h | 1212 # define ADDR_SURF_BANK_HEIGHT_1 0 macro
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D | cikd.h | 1266 # define ADDR_SURF_BANK_HEIGHT_1 0 macro
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D | evergreend.h | 2223 # define ADDR_SURF_BANK_HEIGHT_1 0 macro
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/drivers/gpu/drm/amd/include/asic_reg/bif/ |
D | bif_5_1_enum.h | 964 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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D | bif_5_0_enum.h | 1094 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
D | gmc_8_2_enum.h | 964 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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D | gmc_8_1_enum.h | 1094 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/smu/ |
D | smu_8_0_enum.h | 964 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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D | smu_7_1_0_enum.h | 1123 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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D | smu_7_1_3_enum.h | 1178 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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D | smu_7_1_1_enum.h | 1124 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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D | smu_7_1_2_enum.h | 1142 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
D | uvd_6_0_enum.h | 977 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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D | uvd_5_0_enum.h | 1107 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/dce/ |
D | dce_8_0_enum.h | 1049 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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D | dce_10_0_enum.h | 1669 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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/drivers/gpu/drm/amd/include/asic_reg/oss/ |
D | oss_2_4_enum.h | 1259 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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D | oss_3_0_enum.h | 1393 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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D | oss_3_0_1_enum.h | 1360 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
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