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Searched refs:ADDR_SURF_BANK_HEIGHT_1 (Results 1 – 25 of 32) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c503 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init()
530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init()
537 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init()
548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init()
556 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init()
697 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init()
745 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init()
777 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init()
785 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init()
794 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v6_0_tiling_mode_table_init()
[all …]
Dgfx_v8_0.c2267 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()
2271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()
2295 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()
2299 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()
2459 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()
2463 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()
2479 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()
2487 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()
2491 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()
2648 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v8_0_tiling_mode_table_init()
[all …]
Dgfx_v7_0.c1167 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()
1171 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()
1175 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()
1179 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()
1183 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()
1203 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()
1207 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()
1211 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()
1350 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()
1354 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in gfx_v7_0_tiling_mode_table_init()
[all …]
Dsid.h1210 # define ADDR_SURF_BANK_HEIGHT_1 0 macro
/drivers/gpu/drm/radeon/
Dcik.c2458 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()
2462 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()
2466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()
2470 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()
2474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()
2486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()
2490 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()
2494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()
2498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()
2502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in cik_tiling_mode_table_init()
[all …]
Dsi.c2580 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()
2634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()
2670 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()
2679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()
2715 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()
2724 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()
2795 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()
2849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()
2885 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()
2894 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | in si_tiling_mode_table_init()
[all …]
Dsid.h1212 # define ADDR_SURF_BANK_HEIGHT_1 0 macro
Dcikd.h1266 # define ADDR_SURF_BANK_HEIGHT_1 0 macro
Devergreend.h2223 # define ADDR_SURF_BANK_HEIGHT_1 0 macro
/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_1_enum.h964 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
Dbif_5_0_enum.h1094 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_8_2_enum.h964 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
Dgmc_8_1_enum.h1094 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_8_0_enum.h964 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
Dsmu_7_1_0_enum.h1123 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
Dsmu_7_1_3_enum.h1178 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
Dsmu_7_1_1_enum.h1124 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
Dsmu_7_1_2_enum.h1142 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_enum.h977 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
Duvd_5_0_enum.h1107 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_enum.h1049 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
Ddce_10_0_enum.h1669 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_enum.h1259 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
Doss_3_0_enum.h1393 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator
Doss_3_0_1_enum.h1360 ADDR_SURF_BANK_HEIGHT_1 = 0x0, enumerator

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