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Searched refs:ADF_CSR_RD (Results 1 – 12 of 12) sorted by relevance

/drivers/crypto/qat/qat_common/
Dadf_pf2vf_msg.c90 reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK3); in adf_enable_vf2pf_interrupts()
97 reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK5); in adf_enable_vf2pf_interrupts()
113 reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK3) | in adf_disable_vf2pf_interrupts()
120 reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK5) | in adf_disable_vf2pf_interrupts()
160 val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset); in __adf_iov_putmsg()
176 val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset); in __adf_iov_putmsg()
195 val = ADF_CSR_RD(pmisc_bar_addr, pf2vf_offset); in __adf_iov_putmsg()
246 msg = ADF_CSR_RD(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr)); in adf_vf2pf_req_hndl()
Dadf_transport_access_macros.h122 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
125 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
128 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
Dicp_qat_hal.h137 ADF_CSR_RD(handle->hal_cap_g_ctl_csr_addr_v, csr)
146 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
Dadf_admin.c165 if (ADF_CSR_RD(mailbox, mb_offset) == 1) { in adf_put_admin_msg_sync()
175 if (ADF_CSR_RD(mailbox, mb_offset) == 0) { in adf_put_admin_msg_sync()
Dadf_sriov.c67 ADF_CSR_RD(pmisc_bar_addr, ME2FUNCTION_MAP_A_OFFSET + \
75 ADF_CSR_RD(pmisc_bar_addr, ME2FUNCTION_MAP_B_OFFSET + \
Dadf_vf_isr.c125 msg = ADF_CSR_RD(pmisc_bar_addr, hw_data->get_pf2vf_offset(0)); in adf_pf2vf_bh_handler()
209 v_int = ADF_CSR_RD(pmisc_bar_addr, ADF_VINTSOU_OFFSET); in adf_isr()
Dadf_isr.c117 vf_mask = ((ADF_CSR_RD(pmisc_bar_addr, ADF_ERRSOU5) & in adf_msix_isr_ae()
119 ((ADF_CSR_RD(pmisc_bar_addr, ADF_ERRSOU3) & in adf_msix_isr_ae()
Dadf_accel_devices.h202 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset) macro
Dqat_hal.c462 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
466 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
472 csr_val = ADF_CSR_RD(csr_addr, 0); in qat_hal_init_esram()
/drivers/crypto/qat/qat_c62x/
Dadf_c62x_hw_data.c171 val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
174 val = ADF_CSR_RD(csr, ADF_C62X_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
181 val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i)); in adf_enable_error_correction()
184 val = ADF_CSR_RD(csr, ADF_C62X_CERRSSMSH(i)); in adf_enable_error_correction()
/drivers/crypto/qat/qat_c3xxx/
Dadf_c3xxx_hw_data.c161 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
164 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
171 val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i)); in adf_enable_error_correction()
174 val = ADF_CSR_RD(csr, ADF_C3XXX_CERRSSMSH(i)); in adf_enable_error_correction()
/drivers/crypto/qat/qat_dh895xcc/
Dadf_dh895xcc_hw_data.c183 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
186 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
193 val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i)); in adf_enable_error_correction()
196 val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i)); in adf_enable_error_correction()