/drivers/crypto/qat/qat_common/ |
D | adf_transport_access_macros.h | 131 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 138 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 140 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 144 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 147 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 150 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \ 154 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 156 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 160 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ 163 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \ [all …]
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D | adf_pf2vf_msg.c | 66 ADF_CSR_WR(pmisc_bar_addr, hw_data->get_vintmsk_offset(0), 0x0); in adf_enable_pf2vf_interrupts() 76 ADF_CSR_WR(pmisc_bar_addr, hw_data->get_vintmsk_offset(0), 0x2); in adf_disable_pf2vf_interrupts() 92 ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK3, reg); in adf_enable_vf2pf_interrupts() 99 ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK5, reg); in adf_enable_vf2pf_interrupts() 115 ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK3, reg); in adf_disable_vf2pf_interrupts() 122 ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK5, reg); in adf_disable_vf2pf_interrupts() 171 ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, msg); in __adf_iov_putmsg() 190 ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, msg | int_bit); in __adf_iov_putmsg() 205 ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, val & ~local_in_use_mask); in __adf_iov_putmsg() 250 ADF_CSR_WR(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr), msg); in adf_vf2pf_req_hndl()
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D | adf_hw_arbiter.c | 63 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \ 67 ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \ 71 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \ 76 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
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D | icp_qat_hal.h | 135 ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val) 145 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val) 153 ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val) 155 ADF_CSR_WR(handle->hal_sram_addr_v, addr, val)
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D | adf_admin.c | 171 ADF_CSR_WR(mailbox, mb_offset, 1); in adf_put_admin_msg_sync() 269 ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGUR_OFFSET, reg_val >> 32); in adf_init_admin_comms() 270 ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGLR_OFFSET, reg_val); in adf_init_admin_comms()
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D | adf_sriov.c | 71 ADF_CSR_WR(pmisc_bar_addr, ME2FUNCTION_MAP_A_OFFSET + \ 79 ADF_CSR_WR(pmisc_bar_addr, ME2FUNCTION_MAP_B_OFFSET + \
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D | adf_vf_isr.c | 152 ADF_CSR_WR(pmisc_bar_addr, hw_data->get_pf2vf_offset(0), msg); in adf_pf2vf_bh_handler() 172 ADF_CSR_WR(pmisc_bar_addr, hw_data->get_pf2vf_offset(0), msg); in adf_pf2vf_bh_handler()
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D | adf_accel_devices.h | 198 #define ADF_CSR_WR(csr_base, csr_offset, val) \ macro
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D | qat_hal.c | 468 ADF_CSR_WR(csr_addr, 0, csr_val); in qat_hal_init_esram()
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/drivers/crypto/qat/qat_c62x/ |
D | adf_c62x_hw_data.c | 173 ADF_CSR_WR(csr, ADF_C62X_AE_CTX_ENABLES(i), val); in adf_enable_error_correction() 176 ADF_CSR_WR(csr, ADF_C62X_AE_MISC_CONTROL(i), val); in adf_enable_error_correction() 183 ADF_CSR_WR(csr, ADF_C62X_UERRSSMSH(i), val); in adf_enable_error_correction() 186 ADF_CSR_WR(csr, ADF_C62X_CERRSSMSH(i), val); in adf_enable_error_correction() 197 ADF_CSR_WR(addr, ADF_C62X_SMIAPF0_MASK_OFFSET, in adf_enable_ints() 199 ADF_CSR_WR(addr, ADF_C62X_SMIAPF1_MASK_OFFSET, in adf_enable_ints()
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/drivers/crypto/qat/qat_c3xxx/ |
D | adf_c3xxx_hw_data.c | 163 ADF_CSR_WR(csr, ADF_C3XXX_AE_CTX_ENABLES(i), val); in adf_enable_error_correction() 166 ADF_CSR_WR(csr, ADF_C3XXX_AE_MISC_CONTROL(i), val); in adf_enable_error_correction() 173 ADF_CSR_WR(csr, ADF_C3XXX_UERRSSMSH(i), val); in adf_enable_error_correction() 176 ADF_CSR_WR(csr, ADF_C3XXX_CERRSSMSH(i), val); in adf_enable_error_correction() 187 ADF_CSR_WR(addr, ADF_C3XXX_SMIAPF0_MASK_OFFSET, in adf_enable_ints() 189 ADF_CSR_WR(addr, ADF_C3XXX_SMIAPF1_MASK_OFFSET, in adf_enable_ints()
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/drivers/crypto/qat/qat_dh895xcc/ |
D | adf_dh895xcc_hw_data.c | 185 ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val); in adf_enable_error_correction() 188 ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val); in adf_enable_error_correction() 195 ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val); in adf_enable_error_correction() 198 ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val); in adf_enable_error_correction() 209 ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF0_MASK_OFFSET, in adf_enable_ints() 212 ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF1_MASK_OFFSET, in adf_enable_ints()
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