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Searched refs:APMU_SDH1 (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/mmp/
Dclk-of-pxa168.c44 #define APMU_SDH1 0x58 macro
191 …{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6,…
207 …{PXA168_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh…
Dclk-pxa910.c38 #define APMU_SDH1 0x58 macro
274 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); in pxa910_clk_init()
278 apmu_base + APMU_SDH1, 0x1b, &clk_lock); in pxa910_clk_init()
Dclk-of-pxa910.c43 #define APMU_SDH1 0x58 macro
197 …{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6,…
213 …{PXA910_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh…
Dclk-pxa168.c40 #define APMU_SDH1 0x58 macro
299 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); in pxa168_clk_init()
302 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1, in pxa168_clk_init()
Dclk-of-mmp2.c48 #define APMU_SDH1 0x58 macro
229 …{MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sd…
Dclk-mmp2.c45 #define APMU_SDH1 0x58 macro
344 clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1, in mmp2_clk_init()