1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 Madge Horizon ATM Adapter driver. 4 Copyright (C) 1995-1999 Madge Networks Ltd. 5 6 */ 7 8 /* 9 IMPORTANT NOTE: Madge Networks no longer makes the adapters 10 supported by this driver and makes no commitment to maintain it. 11 */ 12 13 /* too many macros - change to inline functions */ 14 15 #ifndef DRIVER_ATM_HORIZON_H 16 #define DRIVER_ATM_HORIZON_H 17 18 19 #ifdef CONFIG_ATM_HORIZON_DEBUG 20 #define DEBUG_HORIZON 21 #endif 22 23 #define DEV_LABEL "hrz" 24 25 #ifndef PCI_VENDOR_ID_MADGE 26 #define PCI_VENDOR_ID_MADGE 0x10B6 27 #endif 28 #ifndef PCI_DEVICE_ID_MADGE_HORIZON 29 #define PCI_DEVICE_ID_MADGE_HORIZON 0x1000 30 #endif 31 32 // diagnostic output 33 34 #define PRINTK(severity,format,args...) \ 35 printk(severity DEV_LABEL ": " format "\n" , ## args) 36 37 #ifdef DEBUG_HORIZON 38 39 #define DBG_ERR 0x0001 40 #define DBG_WARN 0x0002 41 #define DBG_INFO 0x0004 42 #define DBG_VCC 0x0008 43 #define DBG_QOS 0x0010 44 #define DBG_TX 0x0020 45 #define DBG_RX 0x0040 46 #define DBG_SKB 0x0080 47 #define DBG_IRQ 0x0100 48 #define DBG_FLOW 0x0200 49 #define DBG_BUS 0x0400 50 #define DBG_REGS 0x0800 51 #define DBG_DATA 0x1000 52 #define DBG_MASK 0x1fff 53 54 /* the ## prevents the annoying double expansion of the macro arguments */ 55 /* KERN_INFO is used since KERN_DEBUG often does not make it to the console */ 56 #define PRINTDB(bits,format,args...) \ 57 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 ) 58 #define PRINTDM(bits,format,args...) \ 59 ( (debug & (bits)) ? printk (format , ## args) : 1 ) 60 #define PRINTDE(bits,format,args...) \ 61 ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 ) 62 #define PRINTD(bits,format,args...) \ 63 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 ) 64 65 #else 66 67 #define PRINTD(bits,format,args...) 68 #define PRINTDB(bits,format,args...) 69 #define PRINTDM(bits,format,args...) 70 #define PRINTDE(bits,format,args...) 71 72 #endif 73 74 #define PRINTDD(sec,fmt,args...) 75 #define PRINTDDB(sec,fmt,args...) 76 #define PRINTDDM(sec,fmt,args...) 77 #define PRINTDDE(sec,fmt,args...) 78 79 // fixed constants 80 81 #define SPARE_BUFFER_POOL_SIZE MAX_VCS 82 #define HRZ_MAX_VPI 4 83 #define MIN_PCI_LATENCY 48 // 24 IS TOO SMALL 84 85 /* Horizon specific bits */ 86 /* Register offsets */ 87 88 #define HRZ_IO_EXTENT 0x80 89 90 #define DATA_PORT_OFF 0x00 91 #define TX_CHANNEL_PORT_OFF 0x04 92 #define TX_DESCRIPTOR_PORT_OFF 0x08 93 #define MEMORY_PORT_OFF 0x0C 94 #define MEM_WR_ADDR_REG_OFF 0x14 95 #define MEM_RD_ADDR_REG_OFF 0x18 96 #define CONTROL_0_REG 0x1C 97 #define INT_SOURCE_REG_OFF 0x20 98 #define INT_ENABLE_REG_OFF 0x24 99 #define MASTER_RX_ADDR_REG_OFF 0x28 100 #define MASTER_RX_COUNT_REG_OFF 0x2C 101 #define MASTER_TX_ADDR_REG_OFF 0x30 102 #define MASTER_TX_COUNT_REG_OFF 0x34 103 #define TX_DESCRIPTOR_REG_OFF 0x38 104 #define TX_CHANNEL_CONFIG_COMMAND_OFF 0x40 105 #define TX_CHANNEL_CONFIG_DATA_OFF 0x44 106 #define TX_FREE_BUFFER_COUNT_OFF 0x48 107 #define RX_FREE_BUFFER_COUNT_OFF 0x4C 108 #define TX_CONFIG_OFF 0x50 109 #define TX_STATUS_OFF 0x54 110 #define RX_CONFIG_OFF 0x58 111 #define RX_LINE_CONFIG_OFF 0x5C 112 #define RX_QUEUE_RD_PTR_OFF 0x60 113 #define RX_QUEUE_WR_PTR_OFF 0x64 114 #define MAX_AAL5_CELL_COUNT_OFF 0x68 115 #define RX_CHANNEL_PORT_OFF 0x6C 116 #define TX_CELL_COUNT_OFF 0x70 117 #define RX_CELL_COUNT_OFF 0x74 118 #define HEC_ERROR_COUNT_OFF 0x78 119 #define UNASSIGNED_CELL_COUNT_OFF 0x7C 120 121 /* Register bit definitions */ 122 123 /* Control 0 register */ 124 125 #define SEEPROM_DO 0x00000001 126 #define SEEPROM_DI 0x00000002 127 #define SEEPROM_SK 0x00000004 128 #define SEEPROM_CS 0x00000008 129 #define DEBUG_BIT_0 0x00000010 130 #define DEBUG_BIT_1 0x00000020 131 #define DEBUG_BIT_2 0x00000040 132 // RESERVED 0x00000080 133 #define DEBUG_BIT_0_OE 0x00000100 134 #define DEBUG_BIT_1_OE 0x00000200 135 #define DEBUG_BIT_2_OE 0x00000400 136 // RESERVED 0x00000800 137 #define DEBUG_BIT_0_STATE 0x00001000 138 #define DEBUG_BIT_1_STATE 0x00002000 139 #define DEBUG_BIT_2_STATE 0x00004000 140 // RESERVED 0x00008000 141 #define GENERAL_BIT_0 0x00010000 142 #define GENERAL_BIT_1 0x00020000 143 #define GENERAL_BIT_2 0x00040000 144 #define GENERAL_BIT_3 0x00080000 145 #define RESET_HORIZON 0x00100000 146 #define RESET_ATM 0x00200000 147 #define RESET_RX 0x00400000 148 #define RESET_TX 0x00800000 149 #define RESET_HOST 0x01000000 150 // RESERVED 0x02000000 151 #define TARGET_RETRY_DISABLE 0x04000000 152 #define ATM_LAYER_SELECT 0x08000000 153 #define ATM_LAYER_STATUS 0x10000000 154 // RESERVED 0xE0000000 155 156 /* Interrupt source and enable registers */ 157 158 #define RX_DATA_AV 0x00000001 159 #define RX_DISABLED 0x00000002 160 #define TIMING_MARKER 0x00000004 161 #define FORCED 0x00000008 162 #define RX_BUS_MASTER_COMPLETE 0x00000010 163 #define TX_BUS_MASTER_COMPLETE 0x00000020 164 #define ABR_TX_CELL_COUNT_INT 0x00000040 165 #define DEBUG_INT 0x00000080 166 // RESERVED 0xFFFFFF00 167 168 /* PIO and Bus Mastering */ 169 170 #define MAX_PIO_COUNT 0x000000ff // 255 - make tunable? 171 // 8188 is a hard limit for bus mastering 172 #define MAX_TRANSFER_COUNT 0x00001ffc // 8188 173 #define MASTER_TX_AUTO_APPEND_DESC 0x80000000 174 175 /* TX channel config command port */ 176 177 #define PCR_TIMER_ACCESS 0x0000 178 #define SCR_TIMER_ACCESS 0x0001 179 #define BUCKET_CAPACITY_ACCESS 0x0002 180 #define BUCKET_FULLNESS_ACCESS 0x0003 181 #define RATE_TYPE_ACCESS 0x0004 182 // UNUSED 0x00F8 183 #define TX_CHANNEL_CONFIG_MULT 0x0100 184 // UNUSED 0xF800 185 #define BUCKET_MAX_SIZE 0x003f 186 187 /* TX channel config data port */ 188 189 #define CLOCK_SELECT_SHIFT 4 190 #define CLOCK_DISABLE 0x00ff 191 192 #define IDLE_RATE_TYPE 0x0 193 #define ABR_RATE_TYPE 0x1 194 #define VBR_RATE_TYPE 0x2 195 #define CBR_RATE_TYPE 0x3 196 197 /* TX config register */ 198 199 #define DRVR_DRVRBAR_ENABLE 0x0001 200 #define TXCLK_MUX_SELECT_RCLK 0x0002 201 #define TRANSMIT_TIMING_MARKER 0x0004 202 #define LOOPBACK_TIMING_MARKER 0x0008 203 #define TX_TEST_MODE_16MHz 0x0000 204 #define TX_TEST_MODE_8MHz 0x0010 205 #define TX_TEST_MODE_5_33MHz 0x0020 206 #define TX_TEST_MODE_4MHz 0x0030 207 #define TX_TEST_MODE_3_2MHz 0x0040 208 #define TX_TEST_MODE_2_66MHz 0x0050 209 #define TX_TEST_MODE_2_29MHz 0x0060 210 #define TX_NORMAL_OPERATION 0x0070 211 #define ABR_ROUND_ROBIN 0x0080 212 213 /* TX status register */ 214 215 #define IDLE_CHANNELS_MASK 0x00FF 216 #define ABR_CELL_COUNT_REACHED_MULT 0x0100 217 #define ABR_CELL_COUNT_REACHED_MASK 0xFF 218 219 /* RX config register */ 220 221 #define NON_USER_CELLS_IN_ONE_CHANNEL 0x0008 222 #define RX_ENABLE 0x0010 223 #define IGNORE_UNUSED_VPI_VCI_BITS_SET 0x0000 224 #define NON_USER_UNUSED_VPI_VCI_BITS_SET 0x0020 225 #define DISCARD_UNUSED_VPI_VCI_BITS_SET 0x0040 226 227 /* RX line config register */ 228 229 #define SIGNAL_LOSS 0x0001 230 #define FREQUENCY_DETECT_ERROR 0x0002 231 #define LOCK_DETECT_ERROR 0x0004 232 #define SELECT_INTERNAL_LOOPBACK 0x0008 233 #define LOCK_DETECT_ENABLE 0x0010 234 #define FREQUENCY_DETECT_ENABLE 0x0020 235 #define USER_FRAQ 0x0040 236 #define GXTALOUT_SELECT_DIV4 0x0080 237 #define GXTALOUT_SELECT_NO_GATING 0x0100 238 #define TIMING_MARKER_RECEIVED 0x0200 239 240 /* RX channel port */ 241 242 #define RX_CHANNEL_MASK 0x03FF 243 // UNUSED 0x3C00 244 #define FLUSH_CHANNEL 0x4000 245 #define RX_CHANNEL_UPDATE_IN_PROGRESS 0x8000 246 247 /* Receive queue entry */ 248 249 #define RX_Q_ENTRY_LENGTH_MASK 0x0000FFFF 250 #define RX_Q_ENTRY_CHANNEL_SHIFT 16 251 #define SIMONS_DODGEY_MARKER 0x08000000 252 #define RX_CONGESTION_EXPERIENCED 0x10000000 253 #define RX_CRC_10_OK 0x20000000 254 #define RX_CRC_32_OK 0x40000000 255 #define RX_COMPLETE_FRAME 0x80000000 256 257 /* Offsets and constants for use with the buffer memory */ 258 259 /* Buffer pointers and channel types */ 260 261 #define BUFFER_PTR_MASK 0x0000FFFF 262 #define RX_INT_THRESHOLD_MULT 0x00010000 263 #define RX_INT_THRESHOLD_MASK 0x07FF 264 #define INT_EVERY_N_CELLS 0x08000000 265 #define CONGESTION_EXPERIENCED 0x10000000 266 #define FIRST_CELL_OF_AAL5_FRAME 0x20000000 267 #define CHANNEL_TYPE_AAL5 0x00000000 268 #define CHANNEL_TYPE_RAW_CELLS 0x40000000 269 #define CHANNEL_TYPE_AAL3_4 0x80000000 270 271 /* Buffer status stuff */ 272 273 #define BUFF_STATUS_MASK 0x00030000 274 #define BUFF_STATUS_EMPTY 0x00000000 275 #define BUFF_STATUS_CELL_AV 0x00010000 276 #define BUFF_STATUS_LAST_CELL_AV 0x00020000 277 278 /* Transmit channel stuff */ 279 280 /* Receive channel stuff */ 281 282 #define RX_CHANNEL_DISABLED 0x00000000 283 #define RX_CHANNEL_IDLE 0x00000001 284 285 /* General things */ 286 287 #define INITIAL_CRC 0xFFFFFFFF 288 289 // A Horizon u32, a byte! Really nasty. Horizon pointers are (32 bit) 290 // word addresses and so standard C pointer operations break (as they 291 // assume byte addresses); so we pretend that Horizon words (and word 292 // pointers) are bytes (and byte pointers) for the purposes of having 293 // a memory map that works. 294 295 typedef u8 HDW; 296 297 typedef struct cell_buf { 298 HDW payload[12]; 299 HDW next; 300 HDW cell_count; // AAL5 rx bufs 301 HDW res; 302 union { 303 HDW partial_crc; // AAL5 rx bufs 304 HDW cell_header; // RAW bufs 305 } u; 306 } cell_buf; 307 308 typedef struct tx_ch_desc { 309 HDW rd_buf_type; 310 HDW wr_buf_type; 311 HDW partial_crc; 312 HDW cell_header; 313 } tx_ch_desc; 314 315 typedef struct rx_ch_desc { 316 HDW wr_buf_type; 317 HDW rd_buf_type; 318 } rx_ch_desc; 319 320 typedef struct rx_q_entry { 321 HDW entry; 322 } rx_q_entry; 323 324 #define TX_CHANS 8 325 #define RX_CHANS 1024 326 #define RX_QS 1024 327 #define MAX_VCS RX_CHANS 328 329 /* Horizon buffer memory map */ 330 331 // TX Channel Descriptors 2 332 // TX Initial Buffers 8 // TX_CHANS 333 #define BUFN1_SIZE 118 // (126 - TX_CHANS) 334 // RX/TX Start/End Buffers 4 335 #define BUFN2_SIZE 124 336 // RX Queue Entries 64 337 #define BUFN3_SIZE 192 338 // RX Channel Descriptors 128 339 #define BUFN4_SIZE 1408 340 // TOTAL cell_buff chunks 2048 341 342 // cell_buf bufs[2048]; 343 // HDW dws[32768]; 344 345 typedef struct MEMMAP { 346 tx_ch_desc tx_descs[TX_CHANS]; // 8 * 4 = 32 , 0x0020 347 cell_buf inittxbufs[TX_CHANS]; // these are really 348 cell_buf bufn1[BUFN1_SIZE]; // part of this pool 349 cell_buf txfreebufstart; 350 cell_buf txfreebufend; 351 cell_buf rxfreebufstart; 352 cell_buf rxfreebufend; // 8+118+1+1+1+1+124 = 254 353 cell_buf bufn2[BUFN2_SIZE]; // 16 * 254 = 4064 , 0x1000 354 rx_q_entry rx_q_entries[RX_QS]; // 1 * 1024 = 1024 , 0x1400 355 cell_buf bufn3[BUFN3_SIZE]; // 16 * 192 = 3072 , 0x2000 356 rx_ch_desc rx_descs[MAX_VCS]; // 2 * 1024 = 2048 , 0x2800 357 cell_buf bufn4[BUFN4_SIZE]; // 16 * 1408 = 22528 , 0x8000 358 } MEMMAP; 359 360 #define memmap ((MEMMAP *)0) 361 362 /* end horizon specific bits */ 363 364 typedef enum { 365 aal0, 366 aal34, 367 aal5 368 } hrz_aal; 369 370 typedef enum { 371 tx_busy, 372 rx_busy, 373 ultra 374 } hrz_flags; 375 376 // a single struct pointed to by atm_vcc->dev_data 377 378 typedef struct { 379 unsigned int tx_rate; 380 unsigned int rx_rate; 381 u16 channel; 382 u16 tx_xbr_bits; 383 u16 tx_pcr_bits; 384 #if 0 385 u16 tx_scr_bits; 386 u16 tx_bucket_bits; 387 #endif 388 hrz_aal aal; 389 } hrz_vcc; 390 391 struct hrz_dev { 392 393 u32 iobase; 394 u32 * membase; 395 396 struct sk_buff * rx_skb; // skb being RXed 397 unsigned int rx_bytes; // bytes remaining to RX within region 398 void * rx_addr; // addr to send bytes to (for PIO) 399 unsigned int rx_channel; // channel that the skb is going out on 400 401 struct sk_buff * tx_skb; // skb being TXed 402 unsigned int tx_bytes; // bytes remaining to TX within region 403 void * tx_addr; // addr to send bytes from (for PIO) 404 struct iovec * tx_iovec; // remaining regions 405 unsigned int tx_regions; // number of remaining regions 406 407 spinlock_t mem_lock; 408 wait_queue_head_t tx_queue; 409 410 u8 irq; 411 unsigned long flags; 412 u8 tx_last; 413 u8 tx_idle; 414 415 rx_q_entry * rx_q_reset; 416 rx_q_entry * rx_q_entry; 417 rx_q_entry * rx_q_wrap; 418 419 struct atm_dev * atm_dev; 420 421 u32 last_vc; 422 423 int noof_spare_buffers; 424 u16 spare_buffers[SPARE_BUFFER_POOL_SIZE]; 425 426 u16 tx_channel_record[TX_CHANS]; 427 428 // this is what we follow when we get incoming data 429 u32 txer[MAX_VCS/32]; 430 struct atm_vcc * rxer[MAX_VCS]; 431 432 // cell rate allocation 433 spinlock_t rate_lock; 434 unsigned int rx_avail; 435 unsigned int tx_avail; 436 437 // dev stats 438 unsigned long tx_cell_count; 439 unsigned long rx_cell_count; 440 unsigned long hec_error_count; 441 unsigned long unassigned_cell_count; 442 443 struct pci_dev * pci_dev; 444 struct timer_list housekeeping; 445 }; 446 447 typedef struct hrz_dev hrz_dev; 448 449 /* macros for use later */ 450 451 #define BUF_PTR(cbptr) ((cbptr) - (cell_buf *) 0) 452 453 #define INTERESTING_INTERRUPTS \ 454 (RX_DATA_AV | RX_DISABLED | TX_BUS_MASTER_COMPLETE | RX_BUS_MASTER_COMPLETE) 455 456 // 190 cells by default (192 TX buffers - 2 elbow room, see docs) 457 #define TX_AAL5_LIMIT (190*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER) // 9112 458 459 // Have enough RX buffers (unless we allow other buffer splits) 460 #define RX_AAL5_LIMIT ATM_MAX_AAL5_PDU 461 462 /* multi-statement macro protector */ 463 #define DW(x) do{ x } while(0) 464 465 #define HRZ_DEV(atm_dev) ((hrz_dev *) (atm_dev)->dev_data) 466 #define HRZ_VCC(atm_vcc) ((hrz_vcc *) (atm_vcc)->dev_data) 467 468 /* Turn the LEDs on and off */ 469 // The LEDs bits are upside down in that setting the bit in the debug 470 // register will turn the appropriate LED off. 471 472 #define YELLOW_LED DEBUG_BIT_0 473 #define GREEN_LED DEBUG_BIT_1 474 #define YELLOW_LED_OE DEBUG_BIT_0_OE 475 #define GREEN_LED_OE DEBUG_BIT_1_OE 476 477 #define GREEN_LED_OFF(dev) \ 478 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED) 479 #define GREEN_LED_ON(dev) \ 480 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED) 481 #define YELLOW_LED_OFF(dev) \ 482 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED) 483 #define YELLOW_LED_ON(dev) \ 484 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED) 485 486 typedef enum { 487 round_up, 488 round_down, 489 round_nearest 490 } rounding; 491 492 #endif /* DRIVER_ATM_HORIZON_H */ 493